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? 2004 microchip technology inc. preliminary ds70083g dspic30f data sheet general purpose and sensor families high-performance digital signal controllers
ds70083g-page ii preliminary ? 2004 microchip technology inc. information contained in this publication regarding device applications and the like is in tended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rf pic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pic kit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the cod e protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted wo rk, you may have a right to sue for relief under that act. microchip received iso/ ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona an d mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development syst ems is iso 9001:2000 certified.
? 2004 microchip technology inc. preliminary ds70083g-page 1 dspic30f high performance modified risc cpu: modified harvard architecture c compiler optimized inst ruction set architecture 84 base instructions 24-bit wide instructions, 16-bit wide data path linear program memory addressing up to 4m instruction words linear data memory addr essing up to 64 kbytes up to 144 kbytes on-chip flash program space up to 48k instruction words up to 8 kbytes of on-chip data ram up to 4 kbytes of non-volatile data eeprom 16 x 16-bit working register array three address generation units that enable: - dual data fetch - accumulator write back for dsp operations flexible addressing modes supporting: - indirect, modulo and bit-reversed modes two 40-bit wide accumu lators with optional saturation logic 17-bit x 17-bit single cycle hardware fractional/ integer multiplier single cycle multiply-accumulate (mac) operation 40-stage barrel shifter up to 30 mips operation: - dc to 40 mhz external clock input - 4 mhz-10 mhz oscillator input with pll active (4x, 8x, 16x) up to 41 interrupt sources: - 8 user selectable priority levels vector table with up to 62 vectors: - 54 interrupt vectors - 8 processor exceptions and software traps peripheral features: high current sink/source i/o pins: 25 ma/25 ma up to 5 external interrupt sources timer module with programmable prescaler: - up to five 16-bit ti mers/counters; optionally pair up 16-bit timers into 32-bit timer modules 16-bit capture input functions 16-bit compare/pwm output functions: - dual compare mode available data converter interface (dci) supports common audio codec protocols, including i 2 s and ac?97 3-wire spi? modules (s upports 4 frame modes) i 2 c? module supports multi-master/slave mode and 7-bit/10-bit addressing addressable uart modules supporting: - interrupt on address bit - wake-up on start bit - 4 characters deep tx and rx fifo buffers can bus modules analog features: 12-bit analog-to-digital converter (a/d) with: - 100 ksps conversion rate - up to 16 input channels - conversion available during sleep and idle programmable low voltage detection (plvd) programmable brown-out detection and reset generation note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). dspic30f enhanced flash 16-bit digital signal controllers general purpose and sensor families
dspic30f ds70083g-page 2 preliminary ? 2004 microchip technology inc. special microcontroller features: enhanced flash program memory: - 10,000 erase/write cycle (min.) for industrial temperatur e range, 100k (typical) data eeprom memory: - 100,000 erase/write cycle (min.) for industrial temperatur e range, 1m (typical) self-reprogrammable under software control power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) flexible watchdog timer (wdt) with on-chip low power rc oscillator for reliable operation fail-safe clock monitor operation: - detects clock failure and switches to on-chip low power rc oscillator programmable code protection in-circuit serial programming? (icsp?) via 3 pins and power/ground selectable power management modes: - sleep, idle and alternate clock modes cmos technology: low power, high speed flash technology wide operating voltage range (2.5v to 5.5v) industrial and extend ed temperature ranges low power consumption
? 2004 microchip technology inc. preliminary ds70083g-page 3 dspic30f dspic30f sensor processor family pin diagrams note: for descriptions of individ ual pins, see section 1.0. device pins program memory sram bytes eeprom bytes timer 16-bit input cap output comp/ std pwm a/d 12-bit 100 ksps uart spi ? i 2 c ? bytes instructions dspic30f2011 18 12k 4k 1024 0 3 2 2 8 ch 1 1 1 dspic30f3012 18 24k 8k 2048 1024 3 2 2 8 ch 1 1 1 dspic30f2012 28 12k 4k 1024 0 3 2 2 10 ch 1 1 1 dspic30f3013 28 24k 8k 2048 1024 3 2 2 10 ch 2 1 1 dspic30f2011 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 18-pin soic and pdip dspic30f3012 mclr v ss v dd emud3/an0/v ref +/cn2/rb0 emuc3/an1/v ref -/cn3/rb1 av dd av ss an2/ss1 /lvdin/cn4/rb2 ic2/int2/rd9 emuc2/ic1/int1/rd8 emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 v ss osc2/clko/rc15 osc1/clki v dd sck1/int0/rf6 pgc/emuc/u1rx/sdi1/sda/rf2 pgd/emud/u1tx/sdo1/scl/rf3 an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 an6/ocfa/rb6 emud2/an7/rb7 an8/oc1/rb8 an9/oc2/rb9 cn17/rf4 cn18/rf5 28-pin pdip and soic dspic30f2012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin pdip and soic dspic30f3013 av dd av ss emuc2/ic1/int1/rd8 v ss v dd sck1/int0/rf6 pgc/emuc/u1rx/sdi1/sda/rf2 pgd/emud/u1tx/sdo1/scl/rf3 an6/ocfa/rb6 emud2/an7/rb7 an8/oc1/rb8 an9/oc2/rb9 u2rx/cn17/rf4 u2tx/cn18/rf5 mclr v ss v dd emud3/an0/v ref +/cn2/rb0 emuc3/an1/v ref -/cn3/rb1 an2/ss1 /lvdin/cn4/rb2 ic2/int2/rd9 emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/ u1atx/cn1/rc13 osc2/clko/rc15 osc1/clki an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 av dd av ss emuc2/oc1/ic1/int1/rd0 v ss v dd pgc/emuc/an5/u1rx/sdi1/sda/cn7/rb5 pgd/emud/an4/u1tx/s do1/scl/cn6/rb4 an6/sck1/int0/ocfa/rb6 emud2/an7/oc2/ic2/int2/rb7 mclr an0/v ref +/cn2/rb0 an1/v ref -/cn3/rb1 an2/ss1 /lvdin/cn4/rb2 emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 osc2/clko/rc15 osc1/clki an3/cn5/rb3
dspic30f ds70083g-page 4 preliminary ? 2004 microchip technology inc. pin diagrams (continued) note: for descriptions of individual pins, see section 1.0. 44-pin qfn 44 43 42 41 40 39 38 37 36 35 12 13 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 an8/oc1/rb8 an9/oc2/rb9 u2rx/cn17/rf4 nc u2tx/cn18/rf5 nc v dd nc v ss pgc/emuc/u1rx/sdi1/sda/rf2 nc nc emuc3 / an1/v ref -/cn3/rb1 emud3 / an0/v ref +/cn2/rb0 mclr av dd nc an6/ocfa/rb6 emud2/an7/rb7 an2/s s1 /lvdin/cn4/rb2 nc an3/cn5/rb3 an4/cn6/rb4 an5/cn7/rb5 nc v ss osc1/clki osc2/clko/rc15 pgd/emud/u1tx/sdo1/scl/rf3 sck1/int0/rf6 emuc2/ic1/int1/rd8 nc nc emuc1/sosco/t1ck / u1arx / cn0 / rc14 nc ic2/int2/rd9 v dd 6 22 33 34 nc av ss nc nc emud1/sosci/t2ck / u1atx / cn1 / rc13 v ss nc dspic30f3013
? 2004 microchip technology inc. preliminary ds70083g-page 5 dspic30f dspic30f general purpose controller family pin diagrams note: for descriptions of individ ual pins, see section 1.0. device pins program memory sram bytes eeprom bytes timer 16-bit input cap output comp/std pwm codec interface a/d 12-bit 100 ksps uart spi ? i 2 c ? can bytes instructions dspic30f3014 40/44 24k 8k 2048 1024 3 2 2 ? 13 ch 2 1 1 - dspic30f4013 40/44 48k 16k 2048 1024 5 4 4 ac?97, i 2 s 13 ch 2 1 1 1 dspic30f5011 64 66k 22k 4096 1024 5 8 8 ac?97, i 2 s 16 ch 2 2 1 2 dspic30f6011 64 132k 44k 6144 2048 5 8 8 ? 16 ch 2 2 1 2 dspic30f6012 64 144k 48k 8192 4096 5 8 8 ac?97, i 2 s 16 ch 2 2 1 2 dspic30f5013 80 66k 22k 4096 1024 5 8 8 ac?97, i 2 s 16 ch 2 2 1 2 dspic30f6013 80 132k 44k 6144 2048 5 8 8 ? 16 ch 2 2 1 2 dspic30f6014 80 144k 48k 8192 4096 5 8 8 ac?97, i 2 s 16 ch 2 2 1 2 pgd/emud/an7/rb7 pgc/emuc/an6/ocfa/rb6 c1rx/rf0 c1tx/rf1 ic1/int1/rd8 oc3/rd2 an8/rb8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 dspic30f4013 mclr v dd v ss an0/v ref +/cn2/rb0 an1/v ref -/cn3/rb1 an2/ss1 /lvdin/cn4/rb2 oc4/rd3 emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 osc2/clko/rc15 osc1/clki an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 an3/cn5/rb3 av dd av ss ic2/int2/rd9 v ss v dd emuc3/sck1/rf6 u1rx/sdi1/sda/rf2 emud3/u1tx/sdo1/scl/rf3 v ss v dd u2rx/cn17/rf4 u2tx/cn18/rf5 an12/cofs/rb12 an10/csdi/rb10 an11/csdo/rb11 an9/csck/rb9 emuc2/oc1/rd0 emud2/oc2/rd1 int0/ra11 40-pin pdip pgd/emud/an7/rb7 pgc/emuc/an6/ocfa/rb6 rf0 rf1 ic1/int1/rd8 rd2 an8/rb8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 dspic30f3014 mclr v dd v ss an0/v ref +/cn2/rb0 an1/v ref -/cn3/rb1 an2/ss1 /lvdin/cn4/rb2 rd3 emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 osc2/clko/rc15 osc1/clki an5/cn7/rb5 an4/cn6/rb4 an3/cn5/rb3 av dd av ss ic2/int2/rd9 v ss v dd emuc3/sck1/rf6 u1rx/sdi1/sda/rf2 emud3/u1tx/sdo1/scl/rf3 v ss v dd u2rx/cn17/rf4 u2tx/cn18/rf5 an12/rb12 an10/rb10 an11/rb11 an9/rb9 emuc2/oc1/rd0 emud2/oc2/rd1 int0/ra11 40-pin pdip
dspic30f ds70083g-page 6 preliminary ? 2004 microchip technology inc. pin diagrams (continued) note: for descriptions of individual pins, see section 1.0. 44-pin tqfp 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 emud3/u1tx/sdo1/scl/rf3 emuc3/sck1/rf6 int1/rd8 rd2 v dd emuc1/sosco/t1ck/u1arx/cn0/rc14 nc v ss rd3 ic2/int2/rd1 int0/ra11 an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 an1/v ref -/cn3/rb1 an0/v ref +/cn2/rb0 mclr nc av dd av ss an9/rb9 an10/rb10 an12/rb12 emuc2/oc1/rd0 emud2/oc2/rd1 v dd v ss c1rx/rf0 c1tx/rf1 u2rx/cn17/rf4 u2tx/cn18/rf5 u1rx/sdi1/sda/rf2 an4/cn6/rb4 an5/cn7/rb5 pgc/emuc/an6/ocfa/rb6 pgd/emud/an7/rb7 an8/rb8 nc v dd v ss osc1/clki osc2/clko/rc15 emud1/sosci/t2ck/u1atx/cn1/rc13 dspic30f3014 an11/rb11 nc
? 2004 microchip technology inc. preliminary ds70083g-page 7 dspic30f pin diagrams (continued) note: for descriptions of individ ual pins, see section 1.0. 44-pin tqfp 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 emud3/u1tx/sdo1/scl/rf3 emuc3/sck1/rf6 ic1/int1/rd8 oc3/rd2 v dd emuc1/sosco/t1ck/u1arx/cn0/rc14 nc v ss oc4/rd3 ic2/int2/rd1 int0/ra11 an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 an1/v ref -/cn3/rb1 an0/v ref +/cn2/rb0 mclr nc av dd av ss an9/csck/rb9 an10/csdi/rb10 an12/cofs/rb12 emuc2/oc1/rd0 emud2/oc2/rd1 v dd v ss crx1/rf0 ctx1/rf1 u2rx/cn17/rf4 u2tx/cn18/rf5 u1rx/sdi1/sda/rf2 an4/ic7/cn6/rb4 an5/ic8/cn7/rb5 pgc/emuc/tb6/an6/ocfa/rb6 pgd/emud/tb7/an7/rb7 an8/rb8 nc v dd v ss osc1/clki osc2/clko/rc15 emud1/sosci/t2ck/u1atx/cn1/rc13 dspic30f4013 an11/csdo/rb11 nc
dspic30f ds70083g-page 8 preliminary ? 2004 microchip technology inc. pin diagrams (continued) note: for descriptions of individual pins, see section 1.0. 44-pin qfn dspic30f3014 emud3 / u1tx/sdo1/scl/rf3 emuc3 / sck1/rf6 ic1/int1/rd8 rd2 v dd emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1 / sosci/t2ck/u1atx/cn1/rc13 v ss rd3 ic2/int2/rd9 int0/ra11 an4/cn6/rb4 an5/cn7/rb5 pgc/emuc/an6/ocfa/rb6 pgd/emud / an7/rb7 an8/rb8 osc2/clko/rc15 v dd v dd v ss v ss osc1/clki emuc2/oc1/rd0 emud2/oc2/rd1 v dd v dd v ss c1rx/rf0 c1tx/rf1 u2rx/cn17/rf4 u2tx/cn18/rf5 u1rx/sdi1/sda/rf2 an12/rb12 an3/cn5/rb3 an2/s s1 /lvdin/cn4/rb2 an1/v ref -/cn3/rb1 an0/v ref +/cn2/rb0 mclr an11/rb11 av dd av ss an9/rb9 an10/rb10 nc 44 43 42 41 40 39 38 37 36 35 12 13 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 6 22 33 34
? 2004 microchip technology inc. preliminary ds70083g-page 9 dspic30f pin diagrams (continued) note: for descriptions of individ ual pins, see section 1.0. 44-pin qfn 44 43 42 41 40 39 38 37 36 35 12 13 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 dspic30f4013 6 22 33 34 emud3/u1tx/sdo1/scl/rf3 emuc3/sck1/rf6 int1/rd8 toc3/rd2 v dd emuc1/sosco/t1ck/u1arx/cn0/rc14 emud1/sosci/t2ck/u1atx/cn1/rc13 v ss oc4/rd3 ic2/int2/rd1 int0/ra11 an4/ic7/cn6/rb4 an5/ic8/cn7/rb5 pgc/emuc/tb6/an6/ocfa/rb6 pgd/emud/tb7/an7/rb7 an8/rb8 osc2/clko/rc15 v dd v dd v ss v ss osc1/clki emuc2/oc1/rd0 emud2/oc2/rd1 v dd v dd v ss crx1/rf0 ctx1/rf1 u2rx/cn17/rf4 u2tx/cn18/rf5 u1rx/sdi1/sda/rf2 an12/cofs/rb12 an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 an1/v ref -/cn3/rb1 an0/v ref +/cn2/rb0 mclr an11/csdo/rb11 av dd av ss an9/csck/rb9 an10/csdi/rb10 nc
dspic30f ds70083g-page 10 preliminary ? 2004 microchip technology inc. pin diagrams (continued) note: for descriptions of individual pins, see section 1.0. 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 emuc1/sosco/t1ck/cn0/rc14 emud1/sosci/t4ck/cn1/rc13 emuc2/oc1/rd0 ic4/int4/rd11 ic2/int2/rd9 ic1/int1/rd8 v ss osc2/clko/rc15 osc1/clki v dd scl/rg2 emuc3/sck1/int0/rf6 u1rx/sdi1/rf2 emud3/u1tx/sdo1/rf3 cofs/rg15 t2ck/rc1 t3ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 an1/v ref -/cn3/rb1 an0/v ref +/cn2/rb0 oc8/cn16/rd7 csdo/rg13 csdi/rg12 csck/rg14 v ss c2tx/rg1 c1tx/rf1 c2rx/rg0 emud2/oc2/rd1 oc3/rd2 pgc/emuc/an6/ocfa/rb6 pgd/emud/an7/rb7 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v ss v dd an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 u2tx/cn18/rf5 u2rx/cn17/rf4 sda/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /cn11/rg9 an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 ic3/int3/rd10 v dd c1rx/rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 64-pin tqfp dspic30f5011
? 2004 microchip technology inc. preliminary ds70083g-page 11 dspic30f pin diagrams (continued) note: for descriptions of individ ual pins, see section 1.0. 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 emuc1/sosco/t1ck/cn0/rc14 emud1/sosci/t4ck/cn1/rc13 emuc2/oc1/rd0 ic4/int4/rd11 ic2/int2/rd9 ic1/int1/rd8 v ss osc2/clko/rc15 osc1/clki v dd scl/rg2 emuc3/sck1/int0/rf6 u1rx/sdi1/rf2 emud3/u1tx/sdo1/rf3 rg15 t2ck/rc1 t3ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc/emuc/an1/v ref -/cn3/rb1 pgd/emud/an0/v ref +/cn2/rb0 oc8/cn16/rd7 rg13 rg12 rg14 v ss c2tx/rg1 c1tx/rf1 c2rx/rg0 emud2/oc2/rd1 oc3/rd2 an6/ocfa/rb6 an7/rb7 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v ss v dd an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 u2tx/cn18/rf5 u2rx/cn17/rf4 sda/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /cn11/rg9 an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 ic3/int3/rd10 v dd c1rx/rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 64-pin tqfp dspic30f6011
dspic30f ds70083g-page 12 preliminary ? 2004 microchip technology inc. pin diagrams (continued) note: for descriptions of individual pins, see section 1.0. 1 2 3 4 5 6 7 8 9 10 11 12 13 36 35 34 33 32 31 30 29 28 27 26 64 63 62 61 60 59 58 57 56 14 15 16 17 18 19 20 21 22 23 24 25 emuc1/sosco/t1ck/cn0/rc14 emud1/sosci/t4ck/cn1/rc13 emuc2/oc1/rd0 ic4/int4/rd11 ic2/int2/rd9 ic1/int1/rd8 v ss osc2/clko/rc15 osc1/clki v dd scl/rg2 emuc3/sck1/int0/rf6 u1rx/sdi1/rf2 emud3/u1tx /sdo1/rf3 cofs/rg15 t2ck/rc1 t3ck/rc2 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr v ss v dd an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc/emuc/an1/v ref -/cn3/rb1 pgd/emud/an0/v ref +/cn2/rb0 oc8/cn16/rd7 csdo/rg13 csdi/rg12 csck/rg14 v ss c2tx/rg1 c1tx/rf1 c2rx/rg0 emud2/oc2/rd1 oc3/rd2 an6/ocfa/rb6 an7/rb7 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v ss v dd an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 u2tx/cn18/rf5 u2rx/cn17/rf4 sda/rg3 43 42 41 40 39 38 37 44 48 47 46 50 49 51 54 53 52 55 45 ss2 /cn11/rg9 an5/ic8/cn7/rb5 an4/ic7/cn6/rb4 ic3/int3/rd10 v dd c1rx/rf0 oc4/rd3 oc7/cn15/rd6 oc6/ic6/cn14/rd5 oc5/ic5/cn13/rd4 64-pin tqfp dspic30f6012
? 2004 microchip technology inc. preliminary ds70083g-page 13 dspic30f pin diagrams (continued) note: for descriptions of individ ual pins, see section 1.0. 72 74 73 71 70 69 68 67 66 65 64 63 62 61 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 49 48 47 46 45 44 21 41 40 39 38 37 36 35 34 23 24 25 26 27 28 29 30 31 32 33 dspic30f5013 17 18 19 75 1 57 56 55 54 53 52 51 60 59 58 43 42 76 78 77 79 22 80 ic5/rd12 oc4/rd3 oc3/rd2 emud2/oc2/rd1 csck/rg14 ra7/cn23 ra6/cn22 c2rx/rg0 c2tx/rg1 c1tx/rf1 c1rx/rf0 csdo/rg13 csdi/rg12 oc8/cn16/rd7 oc6/cn14/rd5 emuc2/oc1/rd0 ic4/rd11 ic2/rd9 ic1/rd8 int4/ra15 ic3/rd10 int3/ra14 v ss osc1/clki v dd scl/rg2 u1rx/rf2 u1tx/rf3 emuc1/sosco/t1ck/cn0/rc14 emud1/sosci/cn1/rc13 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2rx/cn17/rf4 ic8/cn21/rd15 u2tx/cn18/rf5 an6/ocfa/rb6 an7/rb7 t3ck/rc2 t4ck/rc3 t5ck/rc4 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr ss2 /cn11/rg9 an4/cn6/rb4 an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc/emuc/an1/cn3/rb1 pgd/emud/an0/cn2/rb0 v ss v dd cofs/rg15 t2ck/rc1 int2/ra13 int1/ra12 an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 v dd v ss oc5/cn13/rd4 ic6/cn19/rd13 sda/rg3 sdi1/rf7 emud3/sdo1/rf8 an5/cn7/rb5 v ss osc2/clko/rc15 oc7/cn15/rd6 emuc3/sck1/int0/rf6 ic7/cn20/rd14 80-pin tqfp
dspic30f ds70083g-page 14 preliminary ? 2004 microchip technology inc. pin diagrams (continued) note: for descriptions of individual pins, see section 1.0. 72 74 73 71 70 69 68 67 66 65 64 63 62 61 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 49 48 47 46 45 44 21 41 40 39 38 37 36 35 34 23 24 25 26 27 28 29 30 31 32 33 17 18 19 75 1 57 56 55 54 53 52 51 60 59 58 43 42 76 78 77 79 22 80 ic5/rd12 oc4/rd3 oc3/rd2 emud2/oc2/rd1 rg14 ra7/cn23 ra6/cn22 c2rx/rg0 c2tx/rg1 c1tx/rf1 c1rx/rf0 rg13 rg12 oc8/cn16/rd7 oc6/cn14/rd5 emuc2/oc1/rd0 ic4/rd11 ic2/rd9 ic1/rd8 int4/ra15 ic3/rd10 int3/ra14 v ss osc1/clki v dd scl/rg2 u1rx/rf2 u1tx/rf3 emuc1/sosco/t1ck/cn0/rc14 emud1/sosci/cn1/rc13 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2rx/cn17/rf4 ic8/cn21/rd15 u2tx/cn18/rf5 an6/ocfa/rb6 an7/rb7 t3ck/rc2 t4ck/rc3 t5ck/rc4 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr ss2 /cn11/rg9 an4/cn6/rb4 an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc/emuc/an1/cn3/rb1 pgd/emud/an0/cn2/rb0 v ss v dd rg15 t2ck/rc1 int2/ra13 int1/ra12 an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 v dd v ss oc5/cn13/rd4 ic6/cn19/rd13 sda/rg3 sdi1/rf7 emud3/sdo1/rf8 an5/cn7/rb5 v ss osc2/clko/rc15 oc7/cn15/rd6 emuc3/sck1/int0/rf6 ic7/cn20/rd14 80-pin tqfp dspic30f6013
? 2004 microchip technology inc. preliminary ds70083g-page 15 dspic30f pin diagrams (continued) note: for descriptions of individ ual pins, see section 1.0. 72 74 73 71 70 69 68 67 66 65 64 63 62 61 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 50 49 48 47 46 45 44 21 41 40 39 38 37 36 35 34 23 24 25 26 27 28 29 30 31 32 33 17 18 19 75 1 57 56 55 54 53 52 51 60 59 58 43 42 76 78 77 79 22 80 ic5/rd12 oc4/rd3 oc3/rd2 emud2/oc2/rd1 csck/rg14 ra7/cn23 ra6/cn22 c2rx/rg0 c2tx/rg1 c1tx/rf1 c1rx/rf0 csdo/rg13 csdi/rg12 oc8/cn16/rd7 oc6/cn14/rd5 emuc2/oc1/rd0 ic4/rd11 ic2/rd9 ic1/rd8 int4/ra15 ic3/rd10 int3/ra14 v ss osc1/clki v dd scl/rg2 u1rx/rf2 u1tx/rf3 emuc1/sosco/t1ck/cn0/rc14 emud1/sosci/cn1/rc13 v ref +/ra10 v ref -/ra9 av dd av ss an8/rb8 an9/rb9 an10/rb10 an11/rb11 v dd u2rx/cn17/rf4 ic8/cn21/rd15 u2tx/cn18/rf5 an6/ocfa/rb6 an7/rb7 t3ck/rc2 t4ck/rc3 t5ck/rc4 sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 mclr ss2 /cn11/rg9 an4/cn6/rb4 an3/cn5/rb3 an2/ss1 /lvdin/cn4/rb2 pgc/emuc/an1/cn3/rb1 pgd/emud/an0/cn2/rb0 v ss v dd cofs/rg15 t2ck/rc1 int2/ra13 int1/ra12 an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 v dd v ss oc5/cn13/rd4 ic6/cn19/rd13 sda/rg3 sdi1/rf7 emud3/sdo1/rf8 an5/cn7/rb5 v ss osc2/clko/rc15 oc7/cn15/rd6 emuc3/sck1/int0/rf6 ic7/cn20/rd14 80-pin tqfp dspic30f6014
dspic30f ds70083g-page 16 preliminary ? 2004 microchip technology inc. table of contents 1.0 device overview ............. .................... .................... .................... .................. .................. .............................. ............... .............. 17 2.0 cpu architecture overview.......... ....................... ...................... ....................... ..................... ................... .................. ................ 21 3.0 memory organization .......... .................... ..................... .................. .................. .................. .................... .................... ................ 35 4.0 address generator units ................ ....................... ...................... ..................... ................... ................... .................... ................ 47 5.0 interrupts .................. .................... .................... ..................... .................. ................. ....................... ....................... .................... 55 6.0 flash program memory ....... .................... ..................... .................... .................. .................. ............................ ............... ........... 63 7.0 data eeprom memory ........... .................... .................... .................... .................. ................. ................. .................. ................ 69 8.0 i/o ports ............ ....................... .................... .................... .................... .................... ....................... ....................... .................... 75 9.0 timer1 module ......... ...................... ..................... .................... .................... ................... ...................... .................... .................. 81 10.0 timer2/3 module ........ .................... ..................... .................... .................... ................... ..................... ..................... .................. 85 11.0 timer4/5 module ....... .................... ..................... .................... .................... ................... ..................... ..................... .................. 91 12.0 input capture module.......... .................... ..................... .................. .................. ................ .................... .................... .................. 95 13.0 output compare module ................ ....................... ...................... ..................... .................... .................... .................. ................ 99 14.0 spi module............. .................... .................... .................... ..................... ................... .............................. .................. .............. 103 15.0 i2c module ............. .................... .................... .................... ..................... ................... .............................. .................. .............. 107 16.0 universal asynchronous receiver trans mitter (uart) module ........ .................... ..................... ................. ............................ 115 17.0 can module ................. ..................... .................... .................... .................. ................. ..................... ..................... .................. 123 18.0 data converter interface (dci) module.. ...................... ...................... .................... .................... ....................... .............. ......... 135 19.0 12-bit analog-to-digital converter (a/d) module ............ ...................... ....................... ................... ..................... ..................... 145 20.0 system integration .......... .................... .................... .................... .................. ................. ................... ..................... .................. 153 21.0 instruction set summary .............. ....................... ...................... .................... ..................... .................... .................. ................ 169 22.0 development support.......... .................... ..................... .................. .................. ................. ............................ ............... ............ 177 23.0 electrical characteristics ............ ...................... ....................... .................... .................... ..................... .................... ................ 183 24.0 packaging information......... .................... ..................... .................. .................. ................ .................... .................... ................ 223 index .................. ....................... .................... .................... .................... ..................... .................... .................. .................. ................ 237 on-line support............ ..................... .................... .................... .................... ................... ...................... ...................... ..................... 243 systems information and upgrade hot line .... ...................... ...................... .................... ................... ................. ................ .............. 243 reader response ............ .................... .................... .................... ..................... ................... .............................. .................. .............. 244 product identification system.... .................... .................... .................. .................. .................. ....................... .................. .................. 245 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your 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? 2004 microchip technology inc. preliminary ds70083g-page 17 dspic30f 1.0 device overview this document contains device family specific information for the dspic30f family of digital signal controller (dsc) devices. the dspic30f devices contain extensive digital signal processor (dsp) functionality within a high performance 16-bit microcontroller (mcu) architecture. figure 1-1 shows a sample device block diagram. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). note: the device(s) depicted in this block diagram are representative of the corresponding device family. other devices of the same family may vary in terms of number of pins and multiplexing of pin functions. typically, smaller devices in the family contain a subset of the peripherals present in the device(s) shown in this diagram.
dspic30f ds70083g-page 18 preliminary ? 2004 microchip technology inc. figure 1-1: dspic30f5013/6013/6014 block diagram an8/rb8 an9/rb9 an10/rb10 an11/rb11 power-up timer oscillator start-up timer por/bor reset watchdog timer instruction decode & control osc1/clki mclr v dd , v ss an4/cn6/rb4 an12/rb12 an13/rb13 an14/rb14 an15/ocfb/cn12/rb15 low voltage detect uart1, int4/ra15 int3/ra14 v ref +/ra10 v ref -/ra9 can2 timing generation can1, an5/cn7/rb5 16 pch pcl 16 program counter alu<16> 16 24 24 24 24 x data bus ir i 2 c dci an6/ocfa/rb6 an7/rb7 pcu 12-bit adc timers sck2/cn8/rg6 sdi2/cn9/rg7 sdo2/cn10/rg8 ss2 /cn11/rg9 u2tx/cn18/rf5 emuc3/sck1/int0/rf6 sdi1/rf7 emud3/sdo1/rf8 input capture module output compare module emuc1/sosco/t1ck/cn0/rc14 emud1/sosci/cn1/rc13 t4ck/rc3 t2ck/rc1 portb c1rx/rf0 c1tx/rf1 u1rx/rf2 u1tx/rf3 c2rx/rg0 c2tx/rg1 scl/rg2 sda/rg3 portg portd 16 16 16 16 x 16 w reg array divide unit engine dsp decode rom latch 16 y data bus effective address x ragu x wagu y agu pgd/emud/an0/cn2/rb0 pgc/emuc/an1/cn3/rb1 an2/ss1 /lvdin/cn4/rb2 an3/cn5/rb3 osc2/clko/rc15 u2rx/cn17/rf4 av dd , av ss uart2 spi2 16 16 16 16 16 porta portc portf 16 16 16 16 8 interrupt controller psv & table data access control block stack control logic loop control logic data latch data latch y data (4 kbytes) ram x data (4 kbytes) ram address latch address latch control signals to various blocks emuc2/oc1/rd0 emud2/oc2/rd1 oc3/rd2 oc4/rd3 oc5/cn13/rd4 oc6/cn14/rd5 oc7/cn15/rd6 oc8/cn16/rd7 ic1/rd8 ic2/rd9 ic3/rd10 ic4/rd11 ic5/rd12 ic6/cn19/rd13 ic7/cn20/rd14 ic8/cn21/rd15 16 csdi/rg12 csdo/rg13 csck/rg14 cofs/rg15 t3ck/rc2 spi1, int1/ra12 int2/ra13 cn23/ra7 cn22/ra6 t5ck/rc4 address latch program memory (144 kbytes) data latch data eeprom (4 kbytes)
? 2004 microchip technology inc. preliminary ds70083g-page 19 dspic30f table 1-1 provides a brief description of device i/o pinouts and the functions that may be multiplexed to a port pin. multiple function s may exist on one port pin. when multiplexing occurs, the peripheral module?s functional requirements may force an override of the data direction of the port pin. table 1-1: pinout i/o descriptions pin name pin type buffer type description an0-an15 i analog analog input channels. an0 and an1 are also used for device programming data and clock inputs, respectively. av dd p p positive supply for analog module. av ss p p ground reference for analog module. clki clko i o st/cmos ? external clock source input. alwa ys associated with osc1 pin function. oscillator crystal output. con nects to crystal or resonator in crystal oscillator mode. optional ly functions as clko in rc and ec modes. always associated with osc2 pin function. cn0-cn23 i st input change notification inputs. can be software programmed for in ternal weak pull-ups on all inputs. cofs csck csdi csdo i/o i/o i o st st st ? data converter interface frame synchronization pin. data converter interface se rial clock input/output pin. data converter interface serial data input pin. data converter interface serial data output pin. c1rx c1tx c2rx c2tx i o i o st ? st ? can1 bus receive pin. can1 bus transmit pin. can2 bus receive pin. can2 bus transmit pin emud emuc emud1 emuc1 emud2 emuc2 emud3 emuc3 i/o i/o i/o i/o i/o i/o i/o i/o st st st st st st st st icd primary communication channel data input/output pin. icd primary communication c hannel clock input /output pin. icd secondary communication channel data input/output pin. icd secondary communication channel clock i nput/output pin. icd tertiary communication ch annel data input/output pin. icd tertiary communication channel clock input/output pin. icd quaternary communication channel data input/output pin. icd quaternary communication channel clock input/output pin. ic1-ic8 i st capture inputs 1 through 8. int0 int1 int2 int3 int4 i i i i i st st st st st external interrupt 0. external interrupt 1. external interrupt 2. external interrupt 3. external interrupt 4. lvdin i analog low voltage detect reference voltage input pin. mclr i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. ocfa ocfb oc1-oc8 i i o st st ? compare fault a input (for co mpare channels 1, 2, 3 and 4). compare fault b input (for co mpare channels 5, 6, 7 and 8). compare outputs 1 through 8. legend: cmos = cmos compatible input or output analog = analog input st = schmitt trigger input with cmos levels o = output i = input p = power
dspic30f ds70083g-page 20 preliminary ? 2004 microchip technology inc. osc1 osc2 i i/o st/cmos ? oscillator crystal input. st buffe r when configured in rc mode; cmos otherwise. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optiona lly functions as clko in rc and ec modes. pgd pgc i/o i st st in-circuit serial progra mming data input/output pin. in-circuit serial programming clock input pin. ra6-ra7 ra9-ra10 ra12-ra15 i/o i/o i/o st st st porta is a bidirectional i/o port. rb0-rb15 i/o st portb is a bidirectional i/o port. rc1-rc4 rc13-rc15 i/o i/o st st portc is a bidirectional i/o port. rd0-rd15 i/o st portd is a bidirectional i/o port. rf0-rf8 i/o st portf is a bidirectional i/o port. rg0-rg3 rg6-rg9 rg12-rg15 i/o i/o i/o st st st portg is a bidirectional i/o port. sck1 sdi1 sdo1 ss1 sck2 sdi2 sdo2 ss2 i/o i o i i/o i o i st st ? st st st ? st synchronous serial clock input/output for spi1. spi1 data in. spi1 data out. spi1 slave synchronization. synchronous serial clock input/output for spi2. spi2 data in. spi2 data out. spi2 slave synchronization. scl sda i/o i/o st st synchronous serial clock input/output for i 2 c. synchronous serial data input/output for i 2 c. sosco sosci o i ? st/cmos 32 khz low power oscillator crystal output. 32 khz low power oscillator cryst al input. st buffer when config- ured in rc mode; cmos otherwise. t1ck t2ck t3ck t4ck t5ck i i i i i st st st st st timer1 external clock input. timer2 external clock input. timer3 external clock input. timer4 external clock input. timer5 external clock input. u1rx u1tx u1arx u1atx u2rx u2tx i o i o i o st ? st ? st ? uart1 receive. uart1 transmit. uart1 alternate receive. uart1 alternate transmit. uart2 receive. uart2 transmit. v dd p ? positive supply for logic and i/o pins. v ss p ? ground reference for logic and i/o pins. v ref + i analog analog voltage re ference (high) input. v ref - i analog analog voltage re ference (low) input. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type description legend: cmos = cmos compatible input or output analog = analog input st = schmitt trigger input wi th cmos levels o = output i = input p = power
? 2004 microchip technology inc. preliminary ds70083g-page 21 dspic30f 2.0 cpu architecture overview 2.1 core overview the core has a 24-bit instruction word. the program counter (pc) is 23-bits wide with the least significant (ls) bit always clear (refer to section 3.1), and the most significant (ms) bit is ignored during normal pro- gram execution, except for certain specialized instruc- tions. thus, the pc can addr ess up to 4m instruction words of user program space. an instruction pre-fetch mechanism is used to help maintain throughput. pro- gram loop constructs, free from loop count manage- ment overhead, are supported using the do and repeat instructions, both of which are interruptible at any point. the working register array consists of 16 x 16-bit regis- ters, each of which can act as data, address or offset registers. one working register (w15) operates as a software stack pointer fo r interrupts and calls. the data space is 64 kbytes (32k words) and is split into two blocks, referred to as x and y data memory. each block has its own in dependent address genera- tion unit (agu). most in structions operate solely through the x memory, ag u, which provides the appearance of a single unified data space. the multiply-accumulate ( mac ) class of dual source dsp instructions operate thro ugh both the x and y agus, splitting the data address space into two parts (see section 3.2). the x and y data space boundary is device specific and cannot be altered by the user. each data word consists of 2 bytes, and most instructions can address data either as words or bytes. there are two methods of accessing data stored in program memory: the upper 32 kbytes of data space memory can be mapped into the lower ha lf (user space) of pro- gram space at any 16k program word boundary, defined by the 8-bit program space visibility page (psvpag) register. this lets any instruction access program space as if it were data space, with a limitation that the access requires an addi- tional cycle. moreover, only the lower 16 bits of each instruction word ca n be accessed using this method. linear indirect access of 32k word pages within program space is also possible using any working register, via table read and write instructions. table read and write inst ructions can be used to access all 24 bits of an instruction word. overhead-free circular buff ers (modulo addressing) are supported in both x and y a ddress spaces. this is pri- marily intended to remove the loop overhead for dsp algorithms. the x agu also supports bit-reversed addressing on destination effective addresse s to greatly simplify input or output data reordering for radix-2 fft algorithms. refer to section 4.0 for details on modulo and bit-reversed addressing. the core supports inheren t (no operand), relative, literal, memory direct, register direct, register indirect, register offset and literal offset addressing modes. instructions are associated with predefined addressing modes, depend ing upon their functional requirements. for most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle. as a result, 3-operand instructi ons are supported, allowing c = a+b operations to be ex ecuted in a single cycle. a dsp engine has been in cluded to significantly enhance the core arithmetic capability and throughput. it features a high speed 17- bit by 17-bit multiplier, a 40-bit alu, two 40-bit saturating accumulators and a 40-bit bidirectional ba rrel shifter. data in the accumula- tor or any working register can be shifted up to 15 bits right, or 16 bits left in a single cycle. the dsp instruc- tions operate seamlessly with all other instructions and have been designed for opti mal real-time performance. the mac class of instructions can concurrently fetch two data operands from memory while multiplying two w registers. to enable this concurrent fetching of data operands, the data space has been split for these instructions and linear fo r all others. this has been achieved in a transparent and flexible manner, by ded- icating certain worki ng registers to ea ch address space for the mac class of instructions. the core does not support a multi-stage instruction pipeline. however, a single stage instruction pre-fetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. most instructions execute in a single cycle with certain exceptions, as outlined in section 2.3. the core features a vectored exception processing structure for traps and inte rrupts, with 62 independent vectors. the exceptions cons ist of up to 8 traps (of which 4 are reserved) and 54 interrupts. each interrupt is prioritized based on a us er assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest), in conjunction wi th a predetermined ?natural order?. traps have fixed prio rities ranging from 8 to 15. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030).
dspic30f ds70083g-page 22 preliminary ? 2004 microchip technology inc. 2.2 programmer?s model the programmer?s model is shown in figure 2-1 and consists of 16 x 16-bit wor king registers (w0 through w15), 2 x 40-bit accumu lators (acca and accb), status register (sr), data table page register (tblpag), program space visibility page register (psvpag), do and repeat registers (dostart, doend, dcount and rcount) and program counter (pc). the working r egisters can act as data, address or offset registers. all registers are memory mapped. w0 acts as the w register for file register addressing. some of these registers have a shadow register asso- ciated with each of them, as shown in figure 2-1. the shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. none of the shadow registers are accessible directly. the following rules apply for transfer of regist ers into and out of shadows. push.s and pop.s w0, w1, w2, w3, sr (dc, n, ov, z and c bits only) are transferred. do instruction dostart, doend, dcount shadows are pushed on loop start, and popped on loop end. when a byte operation is performed on a working reg- ister, only the least significant byte of the target regis- ter is affected. however, a benefit of memory mapped working registers is that both the least and most sig- nificant bytes can be manipulated through byte wide data memory space accesses. 2.2.1 software stack pointer/ frame pointer the dspic ? devices contain a software stack. w15 is the dedicated software stack pointer (sp), and will be automatically modified by exception processing and subroutine calls and returns. however, w15 can be ref- erenced by any instruction in the same manner as all other w registers. this sim plifies the reading, writing and manipulation of the stack pointer (e.g., creating stack frames). w15 is initialized to 0x0800 during a reset. the user may reprogram the sp during initialization to any location within data space. w14 has been dedicated as a stack frame pointer as defined by the lnk and ulnk instructions. however, w14 can be referenced by any instruction in the same manner as all other w registers. 2.2.2 status register the dspic core has a 16-bit status register (sr), the ls byte of which is referred to as the sr low byte (srl) and the ms byte as the sr high byte (srh). see figure 2-1 for sr layout. srl contains all the mcu al u operation status flags (including the z bit), as well as the cpu interrupt prior- ity level status bits, ipl<2:0> and the repeat active status bit, ra. during exception processing, srl is concatenated with the ms byte of the pc to form a complete word value wh ich is then stacked. the upper byte of the stat us register contains the dsp adder/subtracter status bits, the do loop active bit (da) and the digit carry (dc) status bit. most sr bits are read/write. exceptions are: 1. the da bit: da is read and clear only because accidentally setting it could cause erroneous operation. 2. the ra bit: ra is a re ad only bit because acci- dentally setting it could cause erroneous opera- tion. ra is only set on entry into a repeat loop, and cannot be directly cleared by software. 3. the ov, oa, ob and oab bits: these bits are read only and can only be set by the dsp engine overflow logic. 4. the sa, sb and sab bits: these are read and clear only and can only be set by the dsp engine saturation logic. once set, these flags remain set until cleared by the user, irrespective of the results from any subsequent dsp operations. 2.2.2.1 z status bit instructions that use a carry/borrow input ( addc, cpb, subb and subbr) will only be able to clear z (for a non-zero result) and can never set it. a multi- precision sequence of inst ructions, starting with an instruction with no carry/borrow input, will thus auto- matically logically and the su ccessive results of the zero test. all results must be zero for the z flag to remain set by the end of the sequence. all other instructions can set as well as clear the z bit. 2.2.3 program counter the program counter is 23 -bits wide; bit 0 is always clear. therefore, the pc can address up to 4m instruction words. note: in order to protec t against misaligned stack accesses, w15<0> is always clear. note 1: clearing the sab bit will also clear both the sa and sb bits. 2: when the memory mapped status reg- ister (sr) is the destination address for an operation which affects any of the sr bits, data writes are disabled to all bits.
? 2004 microchip technology inc. preliminary ds70083g-page 23 dspic30f figure 2-1: programmer?s model tabpag pc22 pc0 7 0 d0 d15 program counter data table page address status register working registers dsp operand registers w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12/dsp offset w13/dsp write back w14/frame pointer w15/stack pointer dsp address registers ad39 ad0 ad31 dsp accumulators acca accb psvpag 7 0 program space visibility page address z 0 oa ob sa sb rcount 15 0 repeat loop counter dcount 15 0 do loop counter dostart 22 0 do loop start address ipl2 ipl1 splim stack pointer limit register ad15 srl push.s shadow do shadow oab sab 15 0 core configuration register legend corcon da dc ra n tblpag psvpag ipl0 ov w0/wreg srh do loop end address doend 22 c
dspic30f ds70083g-page 24 preliminary ? 2004 microchip technology inc. 2.3 instruction flow there are 8 types of instruction flows: 1. normal one-word, one-cy cle instructions: these instructions take one effective cycle to execute as shown in figure 2-2. figure 2-2: instruction pipeline flow: 1-word, 1-cycle 2. one-word, two-cycle (o r three-cycle) instruc- tions that are flow control instructions: these instructions include the re lative branches, rela- tive call, skips and return s. when an instruction changes the pc (other th an to increment it), the pipelined fetch is discar ded. this causes the instruction to take two effective cycles to exe- cute as shown in figure 2-3. some instructions that change program flow require 3 cycles, such as the return, retfie and retlw instruc- tions, and instructions that skip over 2-word instructions. figure 2-3: instruction pipeline flow: 1-word, 2-cycle t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. mov.b #0x55,w0 fetch 1 execute 1 2. mov.b #0x35,w1 fetch 2 execute 2 3. add.b w0,w1,w2 fetch 3 execute 3 t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. mov #0x55,w0 fetch 1 execute 1 2. btsc w1,#3 fetch 2 execute 2 skip taken 3. add w0,w1,w2 fetch 3 flush 4. bra sub_1 fetch 4 execute 4 5. sub w0,w1,w3 fetch 5 flush 6. instruction @ address sub_1 fetch sub_1
? 2004 microchip technology inc. preliminary ds70083g-page 25 dspic30f 3. one-word, two-cycle instructions that are not flow control instructions: the only instructions of this type are the mov.d (load and store double- word) instructions, as shown in figure 2-4. figure 2-4: instruction pipeline flow: 1-word, 2-cycle mov.d operations 4. table read/write instructions: these instructions will suspend the fetching to insert a read or write cycle to the program me mory. the instruction fetched while executing the table operation is saved for 1 cycle and executed in the cycle immediately after the ta ble operation as shown in figure 2-5. figure 2-5: instruction pipeline flow: 1-wo rd, 2-cycle table operations 5. two-word instructions for call and goto : in these instructions, the fetch after the instruction provides the remainder of the jump or call desti- nation address. these instructions require 2 cycles to execute, 1 cycle to fetch the 2 instruc- tion words (enabled by a high speed path on the second fetch), and 1 cycle to flush the pipeline as shown in figure 2-6. figure 2-6: instruction pipeline flow: 2-word, 2-cycle goto, call t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. mov w0,0x1234 fetch 1 execute 1 2. mov.d [w0++],w1 fetch 2 execute 2 r/w cycle 1 3. mov w1,0x00aa fetch 3 execute 2 r/w cycle2 3a. stall stall execute 3 4. mov 0x0cc, w0 fetch 4 execute 4 t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. mov #0x1234,w0 fetch 1 execute 1 2. tblrdl [w0++],w1 fetch 2 execute 2 3. mov #0x00aa,w1 fetch 3 execute 2 read cycle 3a. table operation bus read execute 3 4. mov #0x0cc,w0 fetch 4 execute 4 t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. mov #0x1234,w0 fetch 1 execute 1 2. goto label fetch 2l update pc 2a. second word fetch 2h nop 3. instruction @ address label fetch label execute label 4. bset w1, #bit3 fetch 4 execute 4
dspic30f ds70083g-page 26 preliminary ? 2004 microchip technology inc. 6. two-word instructions for do : in these instruc- tions, the fetch after t he instruction contains an address offset. this addr ess offset is added to the first instruction address to generate the last loop instruction address. therefore, these instructions require 2 cycles as shown in figure 2-7. figure 2-7: instruction pipel ine flow: 2-word, 2-cycle do, dow 7. instructions that are subj ected to a stall due to a data dependency between the x ragu and x wagu: an additional cycle is inserted to resolve the resource conflict as shown in figure 2-7. instruction stalls caused by data dependencies are further discussed in section 4.0. figure 2-8: instruction pipeline flow: 1- word, 2-cycle with instruction stall 8. interrupt recognition execution: refer to section 6.0 for details on interrupts. t cy 0t cy 1t cy 2t cy 3t cy 4 1. push doend fetch 1 execute 1 2. do label,#count fetch 2l nop 2a. second word fetch 2h execute 2 3. 1st instruction of loop fetch 3 execute 3 t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. mov.b w0,[w1] fetch 1 execute 1 2. mov.b [w1],portb fetch 2 nop 2a. stall (nop) stall execute 2 3. mov.b w0,portb fetch 3 execute 3
? 2004 microchip technology inc. preliminary ds70083g-page 27 dspic30f 2.4 divide support the dspic devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/16-bit signed and unsigned integer divide operations, in the form of single instruction it erative divides. the following instructions and data sizes are supported: 1. divf - 16/16 signed fractional divide 2. div.sd - 32/16 signed divide 3. div.ud - 32/16 unsigned divide 4. div.sw - 16/16 signed divide 5. div.uw - 16/16 unsigned divide the 16/16 divides are similar to the 32/16 (same number of iterations), but the divi dend is either zero-extended or sign-extended during the first iteration. the quotient for all divide inst ructions is stored in w0, and the remainder in w1. div and divf can specify any w register for both th e 16-bit dividend and divisor. all other divides can specif y any w register for the 16-bit divisor, but the 32-b it dividend must be in an aligned w register pair, su ch as w1:w0, w3:w2, etc. the non-restoring divide algorithm requires one cycle for an initial dividend shift (f or integer divides only), one cycle per divisor bit, and a remainder/quotient correc- tion cycle. the correction cycle is the last cycle of the iteration loop but must be performed (even if the remainder is not required) because it may also adjust the quotient. a consequence of this is that divf will also produce a valid remainder (though it is of little use in fractional arithmetic). the divide instructions must be executed within a repeat loop. any other form of execution (e.g., a series of discrete divide in structions) will not function correctly because the inst ruction flow depends on rcount. the divide instruction does not automatically set up the rcount value and it must, therefore, be explicitly and correctly specified in the repeat instruc- tion as shown in table 2-1 ( repeat will execute the tar- get instruction {operand va lue+1} times). the repeat loop count must be setup fo r 18 iterations of the div/ divf instruction. thus, a complete divide operation requires 19 cycles. table 2-1: divide instructions note: the divide flow is in terruptible. however, the user needs to save the context as appropriate. instruction function divf signed fractional divide: wm/wn w0; rem w1 div.sd signed divide: (wm+1:wm)/wn w0; rem w1 div.sw or div.s signed divide: wm/wn w0; rem w1 div.ud unsigned divide: (wm+1:wm)/wn w0; rem w1 div.uw or div.u unsigned divide: wm/wn w0; rem w1
dspic30f ds70083g-page 28 preliminary ? 2004 microchip technology inc. 2.5 dsp engine concurrent operation of the dsp engine with mcu instruction flow is not poss ible, though both the mcu alu and dsp engine resources may be used concur- rently by the same instruction (e.g., ed and edac instructions). the dsp engine consists of a high speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic). data input to the dsp engine is derived from one of the following: 1. directly from the w ar ray (registers w4, w5, w6 or w7) via the x and y data buses for the mac class of instructions ( mac, msc, mpy, mpy.n, ed, edac, clr and movsac ). 2. from the x bus for all other dsp instructions. 3. from the x bus for all mcu instructions which use the barrel shifter. data output from the dsp engi ne is written to one of the following: 1. the target accumulator, as defined by the dsp instruction being executed. 2. the x bus for mac, msc, clr and movsac accumulator writes, where the ea is derived from w13 only. ( mpy, mpy.n, ed and edac do not offer an accumulator write option.) 3. the x bus for all mcu instructions which use the barrel shifter. the dsp engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional da ta. these instructions are add, sub and neg . the dsp engine has various options selected through various bits in the cpu co re configuration register (corcon), as listed below: 1. fractional or integer dsp multiply (if). 2. signed or unsigned dsp multiply (us). 3. conventional or convergent rounding (rnd). 4. automatic saturation on /off for acca (sata). 5. automatic saturation on /off for accb (satb). 6. automatic saturation on/off for writes to data memory (satdw). 7. accumulator saturation mode selection (accsat). a block diagram of the dsp engine is shown in figure 2-9. note: for corcon layout, see table 4-3.
? 2004 microchip technology inc. preliminary ds70083g-page 29 dspic30f figure 2-9: dsp engine block diagram zero backfill sign-extend barrel shifter 40-bit accumulator a 40-bit accumulator b round logic x data bus to/from w array adder saturate negate 32 32 33 16 16 16 16 40 40 40 40 s a t u r a t e y data bus 40 carry/borrow out carry/borrow in 16 40 multiplier/scaler 17-bit
dspic30f ds70083g-page 30 preliminary ? 2004 microchip technology inc. 2.5.1 multiplier the 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (q31) or 32-bit integer results. the respective number representation formats are shown in figure 2-10. unsigned operands are zero-extended in to the 17th bit of the multiplier input value. signed oper ands are sign-extended into the 17th bit of the multiplier input value. the output of the 17 x 17-bit multiplier/sca ler is a 33-bit value which is sign-extended to 40 bits . integer data is inherently represented as a signed two?s complement value, where the msb is defined as a sign bit. generally speaking, the range of an n- bit two?s complement inte- ger is -2 n-1 to 2 n-1 ? 1. for a 16-bit integer, the data range is -32768 ( 0x8000 ) to 32767 ( 0x7fff ) including ? 0 ? (see figure 2-10). for a 32-bit integer, the data range is -2,147,483,648 ( 0x8000 0000 ) to 2,147,483,645 ( 0x7fff ffff ). when the multiplier is configur ed for fractional multipli- cation, the data is represented as a two?s complement fraction, where the msb is defined as a sign bit and the radix point is implied to li e just after the sign bit (qx format). the range of an n-bit two?s complement frac- tion with this implied radi x point is -1.0 to (1 ? 2 1-n ). for a 16-bit fraction, the q15 data range is -1.0 ( 0x8000 ) to 0.999969482 ( 0x7fff ) including ? 0 ? and has a precision of 3.01518x10 -5 . in fractional mode, the 16x16 multiply operation generates a 1.31 product which has a precision of 4.65661 x 10 -10 . figure 2-10: 16-bit integer and fractional modes certain multiply operations always operate on signed data. these include the mac/msc, mpy[.n] and ed[ac] instructions. the 40-bit adder/subtracter may also optionally negate one of its operand inputs to change the result sign (w ithout changing the oper- ands). this is used to creat e a multiply and subtract ( msc ), or multiply and negate ( mpy.n ) operation. in the special case when bo th input operands are 1.15 fractions and equal to 0x8000 (-1 10 ), the result of the multiplication is corrected to 0x7fffffff (as the closest approximation to +1) by hardware before it is used. it should be noted that with the exception of dsp mul- tiplies, the dspic30f alu operates identically on inte- ger and fractional data. namely, an addition of two integers will yield the same result (binary number) as the addition of two fracti onal numbers. the only differ- ence is how the result is interpreted by the user. how- ever, multiplies performed by dsp operations are different. in these instructio ns, data format selection is made with the if bit (corcon<0>) and us bits (corcon<12>), and it must be set accordingly (? 0 ? for fractional mode, ? 1 ? for integer mode in the case of the if bit, and ? 0 ? for signed mode, ? 1 ? for unsigned mode in the case of the us bi t). this is required because of the implied radix point used by dspic30f fractions. in integer mode, multiplying two 16-bit integers produces a 32-bit integer result. however, multiplying two 1.15 values generates a 2.30 result. since the dspic30f uses 1.31 format for the accumulators, a dsp multiply in fractional mode also includ es a left shift by one bit to keep the radix point pro perly aligned. this feature reduces the resolution of the dsp multiplier to 2 -30 , but has no other effect on the computation. different representations of 0x4001 integer: 2 14 2 13 2 12 2 11 .... 2 0 0x4001 = 2 14 + 2 0 = 16385 1.15 fractional: 2 -15 0x4001 = 2 -1 + 2 -15 = 0.500030518 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . 2 -1 2 -2 2 -3 . . . -2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0
? 2004 microchip technology inc. preliminary ds70083g-page 31 dspic30f the same multiplier is used to support the mcu multi- ply instructions which in clude integer 16-bit signed, unsigned and mixed sign mult iplies. additional data paths are provided to allow these instructions to write the result back into the w ar ray and x data bus (via the w array). these paths are placed prior to the data scaler. the if bit in the corcon register, therefore, only affects the result of the mac class of dsp instruc- tions. all other multiply o perations are assumed to be integer operations. if the user executes a mac instruc- tion on fractional data with out clearing the if bit, the result must be explicitly shif ted left by the user program after multiplication in order to obtain the correct result. the mul instruction may be directed to use byte or word sized operands. byte oper ands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the w array. 2.5.2 data accumulators and adder/subtracter the data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. it can select one of two accumulato rs (a or b) as its pre- accumulation source and post-accumulation destina- tion. for the add and lac instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. 2.5.2.1 adder/subtracter, overflow and saturation the adder/subtracter is a 40- bit adder with an optional zero input into one side and either true, or complement data into the other input. in the case of addition, the carry/borrow input is active high and the other input is true data (not complemented), whereas in the case of subtraction, the carry/borrow input is active low and the other input is complement ed. the adder/subtracter generates overflow status bits sa/sb and oa/ob, which are latched and reflecte d in the status register: overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. overflow into guard bits 32 through 39: this is a recoverable overflow. this bit is set whenever all the guard bits bits are not identical to each other. the adder has an additiona l saturation block which controls accumulator data saturation, if selected. it uses the result of the adder , the overflow status bits described above, and th e sata/b (corcon<7:6>) and accsat (corcon<4>) mode control bits to determine when and to what value to saturate. six status register bits have been provided to support saturation and overflow; they are: 1. oa: acca overflowed into guard bits 2. ob: accb overflowed into guard bits 3. sa: acca saturated (bit 31 overflow and saturation) or acca overflowed into guard bits and saturated (bit 39 overflow and saturation) 4. sb: accb saturated (bit 31 overflow and saturation) or accb overflowed into guard bits and saturated (bit 39 overflow and saturation) 5. oab: logical or of oa and ob 6. sab: logical or of sa and sb the oa and ob bits are modified each time data passes through the adder/s ubtracter. when set, they indicate that the most rece nt operation has overflowed into the accumulator guard bits (bits 32 through 39). the oa and ob bits can a lso optionally generate an arithmetic warning trap when set and the correspond- ing overflow trap flag enable bit (ovaten, ovbten) in the intcon1 register (refer to section 5.0) is set. this allows the user to take i mmediate action, for example, to correct system gain. the sa and sb bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. when set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturati on is enabled). when satu- ration is not enabled, sa and sb default to bit 39 over- flow and thus indicate that a catastrophic overflow has occurred. if the covte bit in the intcon1 register is set, sa and sb bits will ge nerate an arithmetic warning trap when saturation is disabled. the overflow and saturation status bits can optionally be viewed in the status regi ster (sr) as the logical or of oa and ob (in bit oa b) and the logical or of sa and sb (in bit sab). this al lows programmers to check one bit in the status regist er to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. this would be useful for complex number arithmetic which typically uses both the accumulators.
dspic30f ds70083g-page 32 preliminary ? 2004 microchip technology inc. the device supports three saturation and overflow modes: 1. bit 39 overflow and saturation: when bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 ( 0x7fffffffff ), or maximally negative 9.31 value ( 0x8000000000 ) into the target accumula- tor. the sa or sb bit is set and remains set until cleared by the user. this is referred to as ?super saturation? and provides protection against erro- neous data, or unexpe cted algorithm problems (e.g., gain calculations). 2. bit 31 overflow and saturation: when bit 31 overflow and saturation occurs, the saturation logic then lo ads the maximally posi- tive 1.31 value ( 0x007fffffff ), or maximally negative 1.31 value ( 0x0080000000 ) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user. when this saturation mode is in ef fect, the guard bits are not used (so the oa, ob or oab bits are never set). 3. bit 39 catastrophic overflow: the bit 39 overflow status bit from the adder is used to set the sa or sb bit which remain set until cleared by the user. no saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). if the covte bit in the intcon1 register is set, a catastrophic overflow can initiate a trap exception. 2.5.2.2 accumulator ?write back? the mac class of instructions (with the exception of mpy, mpy.n, ed and edac ) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. the write is performed across the x bus into combined x and y address space. the following addressing modes are supported: 1. w13, register direct: the rounded contents of the non-target accumulator are written into w13 as a 1.15 fraction. 2. [w13]+=2, register indirect with post-increment: the rounded contents of the non-target accumu- lator are written into th e address pointed to by w13 as a 1.15 fraction. w13 is then incremented by 2 (for a word write). 2.5.2.3 round logic the round logic is a combinational block which per- forms a conventional (bias ed) or convergent (unbi- ased) round function during an accumulator write (store). the round mode is determined by the state of the rnd bit in the corcon register. it generates a 16- bit, 1.15 data value which is passed to the data space write saturation logic. if ro unding is not indicated by the instruction, a truncated 1.15 data value is stored and the ls word is simply discarded. the two rounding modes ar e shown in figure 2-10. conventional rounding takes bit 15 of the accumulator, zero-extends it and adds it to the accxh word (bits 16 through 31 of the accumulator). if the accxl word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xffff ( 0x8000 included), accxh is incremented. if accxl is between 0x0000 and 0x7fff , accxh is left unch anged. a consequence of this algorithm is that over a succession of random rounding operations, the va lue will tend to be biased slightly positive. convergent (or unbiased) r ounding operates in the same manner as conventio nal rounding, except when accxl equals 0x8000 . if this is the case, the ls bit (bit 16 of the accumulator) of accxh is examined. if it is ? 1 ?, accxh is incremented. if it is ? 0 ?, accxh is not modified. assuming that bit 16 is effectively random in nature, this scheme will remove any rounding bias that may accumulate. the sac and sac.r instructions store either a trun- cated ( sac ) or rounded ( sac.r ) version of the contents of the target accumulator to data memory via the x bus (subject to data saturation, see section 2.5.2.4). note that for the mac class of instructions, the accumulator write back operation will function in the same manner, addressing combined mcu (x and y) data space though the x bus. for this class of instructions, the data is always subject to rounding.
? 2004 microchip technology inc. preliminary ds70083g-page 33 dspic30f 2.5.2.4 data space write saturation in addition to adder/subtracte r saturation, writes to data space may also be saturated but without affecting the contents of the source ac cumulator. the data space write saturation logic block accepts a 16-bit, 1.15 frac- tional value from the round logic block as its input, together with overflow stat us from the original source (accumulator) and the 16-bit round adder. these are combined and used to sele ct the appropriate 1.15 fractional value as output to write to data space memory. if the satdw bit in the corcon register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly, for input data greater than 0x007fff , data written to memory is forced to the maximum positive 1.15 value, 0x7fff . for input data less than 0xff8000 , data written to memory is forced to the maximum negative 1.15 value, 0x8000 . the ms bit of the source (bit 39) is used to determine the sign of the operand being tested. if the satdw bit in the corcon register is not set, the input data is always passed through unmodified under all conditions. 2.5.3 barrel shifter the barrel shifter is capable of performing up to 15-bit arithmetic or logic right shifts , or up to 16-bit left shifts in a single cycle. the source can be either of the two dsp accumulators, or the x bus (to support multi-bit shifts of register or memory data). the shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. a positive value will shift the operand right. a negative value will shift the operand left. a value of ? 0 ? will not modify the operand. the barrel shifter is 40-bits wide, thereby obtaining a 40-bit result for dsp shift ope rations and a 16-bit result for mcu shift operations. data from the x bus is pre- sented to the barrel shifter between bit positions 16 to 31 for right shifts, and bit positio ns 0 to 15 for left shifts.
dspic30f ds70083g-page 34 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 35 dspic30f 3.0 memory organization 3.1 program address space the program address space is 4m instruction words. it is addressable by a 24-bit value from either the 23-bit pc, table instruction ea, or data space ea, when pro- gram space is mapped into data space as defined by table 3-1. note that the program space address is incremented by two betw een successive program words in order to provide co mpatibility with data space addressing. user program space access is restricted to the lower 4m instruction word address range ( 0x000000 to 0x7ffffe ) for all accesses other than tblrd/tblwt , which use tblpag<7> to determine user or configura- tion space access. in table 3-1, program space address construction, bit 23 allows access to the device id, the user id and the configuration bits. otherwise, bit 23 is always clear. table 3-1: program space address construction figure 3-1: data access from program space address generation note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). note: the address map shown in figure 3-5 is conceptual, and the actual memory con- figuration may vary across individual devices depending on available memory. access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access user 0 pc<22:1> 0 tblrd/tblwt user (tblpag<7> = 0 ) tblpag<7:0> data ea<15:0> tblrd/tblwt configuration (tblpag<7> = 1 ) tblpag<7:0> data ea<15:0> program space visibility user 0 psvpag<7:0> data ea<14:0> 0 program counter 23 bits 1 psvpag reg 8 bits ea 15 bits program using select tblpag reg 8 bits ea 16 bits using byte 24-bit ea 0 0 1/0 select user/ configuration table instruction program space counter using space select visibility note: program space visibility cannot be used to access bits <23:16> of a word in program memory.
dspic30f ds70083g-page 36 preliminary ? 2004 microchip technology inc. 3.1.1 program space alignment and data access using table instructions this architecture fetches 24-bit wide program memory. consequently, instructio ns are always aligned. however, as the architecture is modified harvard, data can also be present in program space. there are two methods by which program space can be accessed: via special tabl e instructions, or through the remapping of a 16k word program space page into the upper half of data sp ace (see section 3.1.2). the tblrdl and tblwtl instructions offer a direct method of reading or writing the ls word of any address within program space, without going through data space. the tblrdh and tblwth instructions are the only method whereby the upper 8 bits of a program space word can be accessed as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space which contains the ls data word, and tblrdh and tblwth access the space which contains the ms data byte. figure 3-1 shows how the ea is created for table oper- ations and data space accesses (psv = 1 ). here, p<23:0> refers to a program space word, whereas d<15:0> refers to a data space word. a set of table instructions are provided to move byte or word sized data to and from program space. 1. tblrdl: table read low word: read the ls word of the program address; p<15:0> maps to d<15:0>. byte: read one of the ls bytes of the program address; p<7:0> maps to the destination byte when byte select = 0 ; p<15:8> maps to the destination byte when byte select = 1 . 2. tblwtl: table write low (refer to section 6.0 for details on flash programming) 3. tblrdh: table read high word: read the ms word of the program address; p<23:16> maps to d<7:0>; d<15:8> will always be = 0 . byte: read one of the ms bytes of the program address; p<23:16> maps to the destination byte when byte select = 0 ; the destination byte will always be = 0 when byte select = 1 . 4. tblwth: table write high (refer to section 6.0 for details on flash programming) figure 3-2: program data table access (ls word) 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) tblrdl.w tblrdl.b (wn<0> = 1) tblrdl.b (wn<0> = 0)
? 2004 microchip technology inc. preliminary ds70083g-page 37 dspic30f figure 3-3: program data table access (ms byte) 3.1.2 program space visibility from data space the upper 32 kbytes of data space may optionally be mapped into any 16k word program space page. this provides transparent access of stored constant data from x data space without the need to use special instructions (i.e., tblrdl/h , tblwtl/h instructions). program space access through the data space occurs if the ms bit of the data sp ace ea is set and program space visibility is enabled by setting the psv bit in the core control register (c orcon). the functions of corcon are discussed in section 2.5, dsp engine. data accesses to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. note that the upper half of addressable data space is always part of the x data space. therefore, when a dsp operation uses program space mapping to access this memory region, y data space should typically con- tain state (variable) data for dsp operations, whereas x data space should typically contain coefficient (constant) data. although each data space address, 0x8000 and higher, maps directly into a corresponding program memory address (see figure 3-4), only the lower 16 bits of the 24-bit progra m word are used to contain the data. the upper 8 bits should be programmed to force an illegal instruction to maintain machine robust- ness. refer to the progra mmer?s reference manual (ds70030) for details on instruction encoding. note that by incrementi ng the pc by 2 for each program memory word, the ls 15 bits of data space addresses directly map to the ls 15 bits in the corre- sponding program space addresses. the remaining bits are provided by the pr ogram space visibility page register, psvpag<7:0>, as shown in figure 3-4. for instructions that use psv which are executed outside a repeat loop: the following instruct ions will require one instruction cycle in addition to the specified execution time: - mac class of instructions with data operand pre-fetch - mov instructions - mov.d instructions all other instructions wi ll require two instruction cycles in addition to the specified execution time of the instruction. for instructions that use psv which are executed inside a repeat loop: the following instances will require two instruction cycles in addition to the specified execution time of the instruction: - execution in the first iteration - execution in the last iteration - execution prior to exiting the loop due to an interrupt - execution upon re-enter ing the loop after an interrupt is serviced any other iteration of th e repeat loop will allow the instruction accessing data, using psv, to execute in a single cycle. 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) tblrdh.w tblrdh.b (wn<0> = 1) tblrdh.b (wn<0> = 0) note: psv access is temporarily disabled during table reads/writes.
dspic30f ds70083g-page 38 preliminary ? 2004 microchip technology inc. figure 3-4: data space window into program space operation 23 15 0 psvpag (1) 15 15 ea<15> = 0 ea<15> = 1 16 data space ea data space program space 8 15 23 0x0000 0x8000 0xffff 0x21 0x108000 0x10ffff data read upper half of data space is mapped into program space 0x108200 address concatenation bset corcon,#2 ; psv bit set mov #0x21, w0 ; set psvpag register mov w0, psvpag mov 0x8200, w0 ; acces s program memory location ; using a data space access note: psvpag is an 8-bit register, containing bits <22:15 > of the program space address (i.e., it defines the page in program space to which the up per half of data space is being mapped).
? 2004 microchip technology inc. preliminary ds70083g-page 39 dspic30f figure 3-5: sample program space memory map 3.2 data address space the core has two data spaces. the data spaces can be considered either separate (for some dsp instruc- tions), or as one unified li near address range (for mcu instructions). the data spaces are accessed using two address generation units (agus) and separate data paths. 3.2.1 data spaces the x data space is used by all instructions and sup- ports all addressing modes. there are separate read and write data buses. the x read data bu s is the return data path for all instructions that view data space as combined x and y address space. it is also the x address space data path for the dual operand read instructions ( mac class). the x write data bus is the only write path to data space for all instructions. the x data space also suppo rts modulo addressing for all instructions, subject to addressing mode restric- tions. bit-reversed addressing is only supported for writes to x data space. the y data space is used in concert with the x data space by the mac class of instructions ( clr, ed, edac, mac, movsac, mpy, mpy.n and msc ) to provide two concurrent data read paths. no writes occur across the y bus. this class of instructions dedi- cates two w register pointers, w10 and w11, to always address y data space, independent of x data space, whereas w8 and w9 always address x data space. note that during accumula tor write back, the data address space is considered a combination of x and y data spaces, so the write occurs across the x bus. consequently, the write can be to any address in the entire data space. the y data space can only be used for the data pre- fetch operation associated with the mac class of instructions. it also su pports modulo add ressing for automated circular buffers. of course, all other instruc- tions can access the y data address space through the x data path as part of the composite linear space. the boundary between the x and y data spaces is defined as shown in figure 3-8 and is not user pro- grammable. should an ea poin t to data outside its own assigned address space, or to a location outside phys- ical memory, an all zero word /byte will be returned. for example, although y address space is visible by all non- mac instructions using any addressing mode, an attempt by a mac instruction to fetch data from that space using w8 or w9 (x space pointers) will return 0x0000 . reset - target address user memory space 000000 00007e 000002 000080 device configuration user flash program memory 018000 017ffe configuration memory space data eeprom (48k instructions) (4 kbytes) 800000 f80000 registers f8000e f80010 devid (2) fefffe ff0000 fffffe reserved f7fffe reserved 7ff000 7feffe (read ? 0 ?s) 8005fe 800600 unitid (32 instr.) vector tables 8005be 8005c0 reset - goto instruction 000004 reserved 7ffffe reserved 000100 0000fe 000084 alternate vector table reserved interrupt vector table note: these address boundaries may vary from one device to another.
dspic30f ds70083g-page 40 preliminary ? 2004 microchip technology inc. table 3-2: effect of invalid memory accesses all effective addresses are 16 bits wide and point to bytes within the data space. therefore, the data space address range is 64 kbytes or 32k words. 3.2.2 data space width the core data width is 16 bits . all internal registers are organized as 16-bit wide words. data space memory is organized in byte address able, 16-bit wide blocks. 3.2.3 data alignment to help maintain backwa rd compatibility with picmicro ? devices and improve data space memory usage efficiency, the dspic3 0f instruction set supports both word and byte operatio ns. data is aligned in data memory and registers as words, but all data space eas resolve to bytes. data byte reads will read the complete word which contains the by te, using the ls bit of any ea to determine which byte to select. the selected byte is placed onto the ls byte of the x data path (no byte accesses are possible from the y data path as the mac class of instruction can only fetch words). that is, data memory and registers are organized as two parallel byte wide entities with s hared (word) address decode but separate write lines. data byte writes only write to the corresponding side of th e array or register which matches the byte address. as a consequence of this byte accessibility, all effective address calculations (incl uding those generated by the dsp operations which are re stricted to word sized data) are internally scaled to step through word aligned memory. for example, the core would recognize that post-modified register indirect addressing mode [ws++] will result in a valu e of ws+1 for byte operations and ws+2 for word operations. all word accesses must be aligned to an even address. misaligned word data fe tches are not supported so care must be taken when mixing byte and word opera- tions, or translating from 8- bit mcu code. should a mis- aligned read or write be attempted, an address error trap will be generated. if the error occurred on a read, the instruction underway is completed, whereas if it occurred on a write, the inst ruction will be executed but the write will not occur. in either case, a trap will then be executed, allowing the system and/or user to exam- ine the machine state prior to execution of the address fault. figure 3-6: data alignment all byte loads into any w reg ister are loaded into the ls byte. the msb is not modified. a sign-extend ( se ) instruction is provided to allow users to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, users can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions, including the dsp instructions, operate only on words. 3.2.4 data space memory map the data space memory is sp lit into two blocks, x and y data space. a key element of this architecture is that y space is a subset of x space, and is fully contained within x space. in order to provide an apparent linear addressing space, x and y spaces have contiguous addresses. when executing any instruction other than one of the mac class of instructions, the x block consists of the 64- kbyte data address space (including all y addresses). when executing one of the mac class of instructions, the x block consists of the 64-kbyte data address space excluding the y address block (for data reads only). in other words, all other instructions regard the entire data memory as one composite address space. the mac class instructions extract the y address space from data space and address it using eas sourced from w10 and w11. the remaining x data space is addressed using w8 and w9. both address spaces are concurrently accessed only with the mac class instructions. an example data space memory map is shown in figure 3-8. attempted operation data returned ea = an unimplemented address 0x0000 w8 or w9 used to access y data space in a mac instruction 0x0000 w10 or w11 used to access x data space in a mac instruction 0x0000 15 8 7 0 0001 0003 0005 0000 0002 0004 byte1 byte 0 byte3 byte 2 byte5 byte 4 ls byte ms byte
? 2004 microchip technology inc. preliminary ds70083g-page 41 dspic30f 3.2.5 near data space an 8-kbyte ?near? data space is reserved in x address memory space between 0x0000 and 0x1fff , which is directly addressable via a 13-b it absolute address field within all memory direct in structions. the remaining x address space and all of the y address space is addressable indirectly. additionally, the whole of x data space is addressable using mov instructions, which support memory direct addressing with a 16-bit address field. the stack pointer always points to the first available free word and grows from lower addresses towards higher addresses. it pre-dec rements for stack pops and post-increments for stack pushes as shown in figure 3- 7. note that for a pc push during any call instruction, the msb of the pc is zero-e xtended before the push, ensuring that the msb is always clear. 3.2.6 software stack the dspic devices contain a software stack. w15 is used as the stack pointer. there is a stack pointer limit register (splim) associ- ated with the stack pointe r. splim is uninitialized at reset. as is the case for the stack pointer, splim<0> is forced to ? 0 ? because all stack operations must be word aligned. whenever an effective address (ea) is generated using w15 as a source or destination pointer, the address thus generated is compared with the value in splim. if the cont ents of the stack pointer (w15) and the splim regist er are equal and a push operation is performed, a st ack error trap will not occur. the stack error trap will occur on a subsequent push operation. thus, for exam ple, if it is desirable to cause a stack error trap when the stack grows beyond address 0x2000 in ram, initialize the splim with the value, 0x1ffe . similarly, a stack pointer underflow (stack error) trap is generated when the stack po inter address is found to be less than 0x0800 , thus preventing the stack from interfering with the specia l function register (sfr) space. a write to the splim register should not be immediately followed by an indirect read operation using w15. figure 3-7: call stack frame note: a pc push during exception processing will concatenate the srl register to the msb of the pc prior to the push. pc<15:0> 000000000 0 15 w15 (before call ) w15 (after call ) stack grows towards higher address 0x0000 pc<22:16> pop : [--w15] push : [w15++]
dspic30f ds70083g-page 42 preliminary ? 2004 microchip technology inc. figure 3-8: sample data space memory map 0x0000 0x07fe sfr space 0x17fe 0xfffe x data ram (x) ls byte address 16 bits lsb msb ms byte address 0x0001 0x07ff 0x17ff 0xffff x data 0x8001 0x8000 optionally mapped into program memory unimplemented (x) 0x27ff 0x27fe 0x2800 0x2801 0x0801 0x0800 0x1801 0x1800 near data 0x1ffe 0x1fff y data ram (y) 2-kbyte sfr space 8-kbyte sram space 8-kbyte note: the address map shown in figure 3-8 is concep tual, and may vary acro ss individual devices depending on available memory. space
? 2004 microchip technology inc. preliminary ds70083g-page 43 dspic30f figure 3-9: data space for mcu and dsp ( mac class) instructions example sfr space (y space) x space sfr space unused x space x space y space unused unused mac class ops (read) indirect ea from any w indirect ea fr om w8, w9 indirect ea from w10, w11 non- mac class ops (read/write) mac class ops (write)
dspic30f ds70083g-page 44 preliminary ? 2004 microchip technology inc. table 3-3: core register map sfr name address (home) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state w0 0000 w0 / wreg 0000 0000 0000 0000 w1 0002 w1 0000 0000 0000 0000 w2 0004 w2 0000 0000 0000 0000 w3 0006 w3 0000 0000 0000 0000 w4 0008 w4 0000 0000 0000 0000 w5 000a w5 0000 0000 0000 0000 w6 000c w6 0000 0000 0000 0000 w7 000e w7 0000 0000 0000 0000 w8 0010 w8 0000 0000 0000 0000 w9 0012 w9 0000 0000 0000 0000 w10 0014 w10 0000 0000 0000 0000 w11 0016 w11 0000 0000 0000 0000 w12 0018 w12 0000 0000 0000 0000 w13 001a w13 0000 0000 0000 0000 w14 001c w14 0000 0000 0000 0000 w15 001e w15 0000 1000 0000 0000 splim 0020 splim 0000 0000 0000 0000 accal 0022 accal 0000 0000 0000 0000 accah 0024 accah 0000 0000 0000 0000 accau 0026 sign-extension (acca<39>) accau 0000 0000 0000 0000 accbl 0028 accbl 0000 0000 0000 0000 accbh 002a accbh 0000 0000 0000 0000 accbu 002c sign-extension (accb<39>) accbu 0000 0000 0000 0000 pcl 002e pcl 0000 0000 0000 0000 pch 0030 ? ? ? ? ? ? ? ? ? pch 0000 0000 0000 0000 tblpag 0032 ? ? ? ? ? ? ? ?tblpag 0000 0000 0000 0000 psvpag 0034 ? ? ? ? ? ? ? ? psvpag 0000 0000 0000 0000 rcount 0036 rcount uuuu uuuu uuuu uuuu dcount 0038 dcount uuuu uuuu uuuu uuuu dostartl 003a dostartl 0 uuuu uuuu uuuu uuu0 dostarth 003c ? ? ? ? ? ? ? ? ? dostarth 0000 0000 0uuu uuuu doendl 003e doendl 0 uuuu uuuu uuuu uuu0 doendh 0040 ? ? ? ? ? ? ? ? ? doendh 0000 0000 0uuu uuuu sr 0042 oa ob sa sb oab sab da dc ipl2 ipl1 ipl0 ra n ov z c 0000 0000 0000 0000 legend: u = uninitialized bit
? 2004 microchip technology inc. preliminary ds70083g-page 45 dspic30f note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. corcon 0044 ? ? ? us edt dl2 dl1 dl0 sata satb satdw accsat ipl3 psv rnd if 0000 0000 0010 0000 modcon 0046 xmoden ymoden ? ? bwm<3:0> ywm<3:0> xwm<3:0> 0000 0000 0000 0000 xmodsrt 0048 xs<15:1> 0 uuuu uuuu uuuu uuu0 xmodend 004a xe<15:1> 1 uuuu uuuu uuuu uuu1 ymodsrt 004c ys<15:1> 0 uuuu uuuu uuuu uuu0 ymodend 004e ye<15:1> 1 uuuu uuuu uuuu uuu1 xbrev 0050 bren xb<14:0> uuuu uuuu uuuu uuuu disicnt 0052 ? ? disicnt<13:0> 0000 0000 0000 0000 table 3-3: core register map (continued) sfr name address (home) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state legend: u = uninitialized bit
dspic30f ds70083g-page 46 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 47 dspic30f 4.0 address generator units the dspic core contains two independent address generator units: the x agu and y agu. further, the x agu has two parts: x ragu (read agu) and x wagu (write agu). the x ragu and x wagu sup- port byte and word sized da ta space reads and writes for both mcu and dsp instructions. the y agu sup- ports word sized data reads for the dsp mac class of instructions only. they are each capable of supporting two types of data addressing: linear addressing modulo (circular) addressing in addition, the x wagu can support: bit-reversed addressing linear and modulo data addressing modes can be applied to data space or program space. bit-reversed addressing is only applicable to data space addresses. 4.1 data space organization although the data space memo ry is organized as 16-bit words, all effective addresses (eas) are byte addresses. instructions can thus access individual bytes as well as properly aligned words. word addresses must be aligned at even boundaries. mis- aligned word accesses are not supported, and if attempted, will initiate an address error trap. when executing instructions which require just one source operand to be fetch ed from data space, the x ragu and x wagu are used to calculate the effective address. the x ragu and x wagu can generate any address in the 64-kbyte data space. they support all mcu addressing modes and modulo addressing for low overhead circular buffer s. the x wagu also sup- ports bit-reversed addre ssing to facilitate fft data reorganization. when executing instructions which require two source operands to be concurrently fetched (i.e., the mac class of dsp instructions), both the x ragu and y agu are used simultaneously and the data space is split into two independent address spaces, x and y. the y agu sup- ports register indirect post-modified and modulo addressing only. in the split data space mode, some w register address pointers are dedicated to x ragu, and others to y agu. the eas of each operand must, therefore, be restricted within different address spaces. if they are not, one of the eas will be outside the address space of the corresponding data sp ace (and will fetch the bus default value, 0x0000 ). 4.2 instruction addressing modes the addressing modes in ta ble 4-1 form the basis of the addressing modes optimized to support the specific features of individual instructions. the addressing modes provided in the mac class of instructions are somewhat different from thos e in the other instruction types. some addressing mode comb inations may lead to a one-cycle stall during instru ction execution, or are not allowed, as discussed in section 4.3. table 4-1: fundamental addressing modes supported note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). note: the data write phase of the mac class of instructions does not split x and y address space. the write ea is calculated using the x wagu and the data space is configured for full 64-kbyte access. addressing mode description file register direct the address of the file register is specified explicitly. register direct the contents of a register are accessed directly. register indirect the contents of wn forms the ea. register indirect post-modified the contents of wn forms the ea. wn is pos t-modified (incremented or decremented) by a constant value. register indirect pre-modified wn is pre-modified (incremented or decrem ented) by a signed constant value to form the ea. register indirect with register offs et the sum of wn and wb forms the ea. register indirect with literal offset t he sum of wn and a li teral forms the ea.
dspic30f ds70083g-page 48 preliminary ? 2004 microchip technology inc. 4.2.1 file register instructions most file register instructio ns use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory. these memory locations are known as file registers. most file register instructions employ a working register , w0, which is denoted as wreg in these instructions. the destination is typically either the same file register or wreg (with the excep- tion of the mul instruction), which writes the result to a register or register pair. the mov instruction can use a 16-bit address field. 4.2.2 mcu instructions the three-operand mcu instructions are of the form: operand 3 = operand 1 operand 2 where operand 1 is always a working register (i.e., the addressing mode can only be register direct) which is referred to as wb. oper and 2 can be the w register fetched from data memory or 5-bit literal. in two- operand instructions, the resu lt location is the same as that of one of the operan ds. certain mcu instructions are one-operand operations. the following addressing modes are supported by mcu instructions: register direct register indirect register indirect post-modified register indirect pre-modified 5-bit or 10-bit literal 4.2.3 move and accumulator instructions move instructions and t he dsp accumulator class of instructions provide a great er degree of addressing flexibility than other instru ctions. in addition to the addressing modes supported by most mcu instruc- tions, move and accumulator instructions also support register indirect with register offset addressing mode, also referred to as register indexed mode. in summary, the following addressing modes are supported by move and accumulator instructions: register direct register indirect register indirect post-modified register indirect pre-modified register indirect with register offset (indexed) register indirect with literal offset 8-bit literal 16-bit literal 4.2.4 mac instructions the dual source operand dsp instructions ( clr, ed, edac, mac, mpy, mpy.n, movsac and msc ), also referred to as mac instructions, utilize a simplified set of addressing modes to allow the user to effectively manipulate the data pointers through register indirect tables. the 2 source operand pre-fe tch registers must be a member of the set {w8, w9, w10, w11}. for data reads, w8 and w9 will always be directed to the x ragu and w10 and w11 will always be directed to the y agu. the effective addresses generated (before and after modification) must, ther efore, be valid addresses within x data space for w8 and w9 and y data space for w10 and w11. in summary, the following addressing modes are supported by the mac class of instructions: register indirect register indirect post-modified by 2 register indirect post-modified by 4 register indirect post-modified by 6 register indirect with register offset (indexed) 4.2.5 other instructions besides the various addressi ng modes outlined above, some instructions use litera l constants of various sizes. for example, bra (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the disi instruction uses a 14-bit unsigned literal field. in some instructions, such as add acc , the source of an operand or re sult is implied by the opcode itself. certain operations, such as nop , do not have any operands. note: not all instructions support all the addressing modes give n above. individual instructions may support different subsets of these addressing modes. note: for the mov instructions, the addressing mode specified in the instruction can differ for the source and destination ea. however, the 4-bit wb (register offset) field is shared betwee n both source and destination (but typically only used by one). note: not all instructions support all the addressing modes given above. individual instructions may support different subsets of these addressing modes. note: register indirect with register offset addressing is only available for w9 (in x space) and w11 (in y space).
? 2004 microchip technology inc. preliminary ds70083g-page 49 dspic30f 4.3 instruction stalls 4.3.1 introduction in order to maximize data space, ea calculation and operand fetch time, the x data space read and write accesses are partially pipelined. the latter half of the read phase overlaps the firs t half of the write phase of an instruction, as shown in section 2.0. address register data dependencies, also known as ?read after write? (raw) dependencies may, there- fore, arise between successi ve read and write opera- tions using common regist ers. they occur across instruction boundaries and are detected by the hardware. an example of a raw dependency is a write operation (in the current instruction) that modifies w5, followed by a read operation (in the next instruction) that uses w5 as a source address point er. w5 will not be valid for the read operation until th e earlier write completes. this problem is resolved by stalling the instruction exe- cution for one instruction cycle, thereby allowing the write to complete before th e next read is started. 4.3.2 raw dependency detection during the instruction pre-decode, the core determines if any address register d ependency is imminent across an instruction boundary. the stall detection logic com- pares the w register (if any) used for the destination ea of the instruction currently being executed, with the w register to be used by the source ea (if any) of the pre- fetched instruction. as the w registers are also memory mapped, the stall detection logic also derives an sfr address from the w register being used by the destina- tion ea, and determines whet her this address is being issued during the write phase of the instruction currently being executed. when it observes a match between the destination and source registers, a set of rules is applied to decide whether or not to stall t he instruction by one cycle. table 4-2 lists out the va rious raw conditions which cause an instruction execution stall. table 4-2: raw dependency rules (detection by hardware) destination addressing mode using wn source addressing mode using wn status examples (wn = w2) direct direct no stall add.w w0, w1, w2 mov.w w2, w3 direct indirect stall add.w w0, w1, w2 mov.w [w2], w3 direct indirect with pre- or post-modification stall add.w w0, w1, w2 mov.w [w2++], w3 indirect direct no stall add.w w0, w1, [w2] mov.w w2, w3 indirect indirect no stall add.w w0, w1, [w2] mov.w [w2], w3 indirect indirect stall add.w w0, w1, [w2] ; w2=0x0004 (mapped w2) mov.w [w2], w3 ; ( i.e. if w2 = addr. of w2) indirect indirect with pre- or post-modification no stall add.w w0, w1, [w2] mov.w [w2++], w3 indirect indirect with pre- or post-modification stall add.w w0, w1, [w2] ; w2=0x0004 (mapped w2) mov.w [w2++], w3 ; ( i.e. if w2 = addr. of w2) indirect with pre- or post-modification direct no stall add.w w0, w1, [w2++] mov.w w2, w3 indirect with pre- or post-modification indirect stall add.w w0, w1, [w2++] mov.w [w2], w3 indirect with pre- or post-modification indirect with pre- or post-modification stall add.w w0, w1, [w2++] mov.w [w2++], w3
dspic30f ds70083g-page 50 preliminary ? 2004 microchip technology inc. 4.4 modulo addressing modulo addressing is a meth od of providing an auto- mated means to support cir cular data buffers using hardware. the objective is to remove the need for soft- ware to perform data address boundary checks when executing tightly looped code, as is typical in many dsp algorithms. modulo addressing can operat e in either data or pro- gram space (since the data pointer mechanism is essentially the same for both ). one circular buffer can be supported in each of the x (which also provides the pointers into program spac e) and y data spaces. mod- ulo addressing can operate on any w register pointer. however, it is not advisable to use w14 or w15 for mod- ulo addressing since thes e two registers are used as the stack frame pointer and stack pointer, respectively. in general, any particular circular buffer can only be configured to operate in one direction, as there are cer- tain restrictions on the buffer start address (for incre- menting buffers), or end address (for decrementing buffers) based upon the direction of the buffer. the only exception to the usage restrictions is for buff- ers which have a power-of-2 length. as these buffers satisfy the start and end address criteria, they may operate in a bidirectional mode (i.e., address boundary checks will be performed on both the lower and upper address boundaries). 4.4.1 start and end address the modulo addressing scheme requires that a starting and an ending address be s pecified and loaded into the 16-bit modulo buffer addr ess registers: xmodsrt, xmodend, ymodsrt, ymodend (see table 3-3). if the length of an incrementing buffer is greater than m= 2 n-1 , but not greater than m = 2 n bytes, then the last ?n? bits of the data buffer start address must be zeros. there are no such restrictions on the end address of an incrementing buffer. for example, if the buffer size (modulus valu e) is chosen to be 100 bytes ( 0x64 ), then the buffer start address for an increment- ing buffer must contain 7 least significant zeros. valid start addresses may, therefore, be 0xxx00 and 0xxx80 , where ? x ? is any hexadecimal value. adding the buffer length to this value and subtracting ? 1 ? will give the end address to be written into x/ymodend. for example, if the start address was chosen to be 0x2000 , then the x/ymod end would be set to ( 0x2000 + 0x0064 ? 1) = 0x2063 . in the case of a decrementing buffer, the last ?n? bits of the data buffer end address must be ones. there are no such restrictions on th e start address of a decre- menting buffer. for example, if the buffer size (modulus value) is chosen to be 100 bytes ( 0x64 ), then the buffer end address for a decrementing buffer must contain 7 least significant ones. valid end addresses may, therefore, be 0xxxff and 0xxx7f , where ? x ? is any hexadecimal value. subtract ing the buffer length from this value and adding 1 will gi ve the start address to be written into x/ymodsrt. for example, if the end address was chosen to be 0x207f , then the start address would be ( 0x207f ? 0x0064 + 1) = 0x201c , which is the first physical address of the buffer. the length of a circular buffer is not directly specified. it is determined by the difference between the corre- sponding start and end addresses. the maximum pos- sible length of the circular buffer is 32k words (64 kbytes). a write operation to the modcon register should not be immediately followed by an indirect read operation using any w register. note: the start and end addresses are the first and last byte addresses of the buffer (irre- spective of whether it is a word or byte buffer, or an increasing or decreasing buffer). moreover, the start address must be even and the end address must be odd (for both word and byte buffers). note: ?start address? refers to the smallest address boundary of the circular buffer. the first access of the buffer may be at any address within the modulus range (see section 4.4.4). note: y space modulo addressing ea calcula- tions assume word si zed data (ls bit of every ea is always clear). note 1: using a pop instruction to pop the con- tents of the top-of-stack (tos) location into modcon also constitutes a write to modcon. therefore, the instruction immediately following such a pop cannot be any instruction pe rforming an indirect read operation. 2: it should be noted that some instructions perform an indirect read operation implicitly. these are: pop, return, retfie, retlw and ulnk .
? 2004 microchip technology inc. preliminary ds70083g-page 51 dspic30f 4.4.2 w address register selection the modulo and bit-reversed addressing control reg- ister modcon<15:0> contains enable flags as well as a w register field to spe cify the w address registers. the xwm and ywm fields select which registers will operate with modulo addressing. if xwm = 15 , x ragu and x wagu modulo addressing is disabled. similarly, if ywm = 15 , y agu modulo addressing is disabled. the x address space pointer w register (xwm), to which modulo addressing is to be applied, is stored in modcon<3:0> (see table 3-3). modulo addressing is enabled for x data space when xwm is set to any value other than ? 15 ? and the xmoden bit is set at modcon<15>. the y address space pointer w register (ywm), to which modulo addressing is to be applied, is stored in modcon<7:4>. modulo addressing is enabled for y data space when ywm is set to any value other than ? 15 ? and the ymoden bit is set at modcon<14>. figure 4-1: incrementing buffer modulo addressing operation example note: the xmodsrt and xmodend registers and the xwm register selection are shared between x ragu and x wagu. 0x1100 0x1163 start addr = 0x1100 end addr = 0x1163 length = 0x0032 words byte address mov #0x1100,w0 mov w0,xmodsrt ;set modulo start address mov #0x1163,w0 mov w0,modend ;set modulo end address mov #0x8001,w0 mov w0,modcon ;enable w 1, x agu for modulo mov #0x0000,w0 ;w0 holds buffer fill value mov #0x1110,w1 ;point w1 to buffer do again,#0x31 ;fill th e 50 buffer locations mov w0,[w1++] ;fill the next location again: inc w0,w0 ;incr ement the fill value
dspic30f ds70083g-page 52 preliminary ? 2004 microchip technology inc. figure 4-2: decrementing buffer modulo addressing operation example 0x11d0 0x11ff start addr = 0x11d0 end addr = 0x11ff length = 0x0018 words byte address mov #0x11d0,w0 mov #0,xmodsrt ;set modulo start address mov 0x11ff,w0 mov w0,xmodend ;set modulo end address mov #0x8001,w0 mov w0,modcon ;enable w 1, x agu for modulo mov #0x000f,w0 ;w0 ho lds buffer fill value mov #0x11e0,w1 ;point w1 to buffer do again,#0x17 ;fill the 24 buffer locations mov w0,[w1--] ;fill the next location again: dec w0,w0 ; decrement the fill value
? 2004 microchip technology inc. preliminary ds70083g-page 53 dspic30f 4.4.3 modulo addressing applicability modulo addressing can be applied to the effective address (ea) calculation as sociated with any w regis- ter. it is important to real ize that the address bound- aries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decre- menting buffers) boundary a ddresses (not just equal to). address changes may, t herefore, jump over bound- aries and still be adjusted co rrectly (see section 4.4.4 for restrictions). 4.4.4 modulo addressing restrictions for an incrementing buffer, the circular buffer start address (lower boundary) is ar bitrary but must be at a ?zero? power-of-two boundar y (see section 4.4.1). for a decrementing buffer, the ci rcular buffer end address is arbitrary but must be at a ?ones? boundary. there are no restrictions regarding how much an ea calculation can exceed th e address boundary being checked and still be successfully corrected. once configured, the direction of successive addresses into a buffer should not be changed. although all eas will continue to be generated cor- rectly, irrespective of offset sign, only one address boundary is checked for each type of buffer. thus, if a buffer is set up to be an incrementing buffer by choos- ing an appropriate starting address, then correction of the effective address will be performed by the agu at the upper address boundary, but no address correction will occur if the ea cro sses the lower address bound- ary. similarly, for a decr ementing boundary, address correction will be performed by the agu at the lower address boundary, but no address correction will take place if the ea crosses the upper address boundary. the circular buffer pointer may be freely modified in both directions without a possibility of out-of-range address access only when th e start address satisfies the condition for an incrementi ng buffer (last ?n? bits are zeroes) and the end address satisfies the condition for a decrementing buffer (last ?n ? bits are ones). thus, the modulo addressing capability is truly bidirectional only for modulo-2 length buffers. 4.5 bit-reversed addressing bit-reversed addressing is in tended to simplify data re- ordering for radix-2 fft algorithms. it is supported by the x wagu only (i.e., for data writes only). the modifier, which may be a constant value or register contents, is regarded as having its bit order reversed. the address source and destination ar e kept in normal order. thus, the only operand requiring reversal is the modifier. 4.5.1 bit-reversed addressing implementation bit-reversed addressing is enabled when: 1. bwm (w register selection) in the modcon register is any va lue other than ? 15 ? (the stack cannot be accessed using bit-reversed addressing) and 2. the bren bit is set in the xbrev register and 3. the addressing mode used is register indirect with pre-increment or post-increment. if the length of a bit-reversed buffer is m = 2 n bytes, then the last ?n? bits of the data buffer start address must be zeros. xb<14:0> is the bit-reversed address modifier or ?pivot point? which is typically a co nstant. in the case of an fft computation, its value is equal to half of the fft data buffer size. when enabled, bit-reversed addressing will only be executed for register indi rect with pre-increment or post-increment addressing and word sized data writes. it will not function for any other addressing mode or for byte sized data, and normal addresses will be gener- ated instead. when bit-reve rsed addressing is active, the w address pointer will always be added to the address modifier (xb) and the offset associated with the register indirect addr essing mode will be ignored. in addition, as word sized data is a requirement, the ls bit of the ea is ignore d (and always clear). if bit-reversed addressing has already been enabled by setting the bren (xbrev<15>) bit, then a write to the xbrev register should not be immediately followed by an indirect read operation using the w register that has been designated as the bit-reversed pointer. note: the modulo corrected effective address is written back to the register only when pre- modify or post-modify addressing mode is used to compute the effective address. when an address offset (e.g., [w7+w2]) is used, modulo address correction is per- formed but the contents of the register remain unchanged. note: all bit-reversed ea calculations assume word sized data (ls bit of every ea is always clear). the xb value is scaled accordingly to generate compatible (byte) addresses. note: modulo addressing and bit-reversed addressing should not be enabled together. in the event that the user attempts to do this, bit-reversed addressing will assume priority when active for the x wagu, and x wagu modulo addressing will be disabled. however, modulo addressing will continue to function in the x ragu.
dspic30f ds70083g-page 54 preliminary ? 2004 microchip technology inc. figure 4-3: bit-reversed address example table 4-3: bit-reversed address sequence (16-entry) table 4-4: bit-reversed address modifier values normal address bit-reversed address a3 a2 a1 a0 decimal a3 a2 a1 a0 decimal 0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0011 3 1100 12 0100 4 0010 2 0101 5 1010 10 0110 6 0110 6 0111 7 1110 14 1000 8 0001 1 1001 9 1001 9 1010 10 0101 5 1011 11 1101 13 1100 12 0011 3 1101 13 1011 11 1110 14 0111 7 1111 15 1111 15 buffer size (words) xb<14:0> bit-r eversed address modifier value 32768 0x4000 16384 0x2000 8192 0x1000 4096 0x0800 2048 0x0400 1024 0x0200 512 0x0100 256 0x0080 128 0x0040 64 0x0020 32 0x0010 16 0x0008 8 0x0004 4 0x0002 2 0x0001 b3 b2 b1 0 b2 b3 b4 0 bit locations swapped left-to-right around center of binary value bit-reversed address xb = 0x0008 for a 16-word bit-reversed buffer b7 b6 b5 b1 b7 b6 b5 b4 b11 b10 b9 b8 b11 b10 b9 b8 b15 b14 b13 b12 b15 b14 b13 b12 sequential address pivot point
? 2004 microchip technology inc. preliminary ds70083g-page 55 dspic30f 5.0 interrupts the dspic30f sensor and general purpose family has up to 41 interrupt sources and 4 processor excep- tions (traps) which must be arbitrated based on a priority scheme. the cpu is responsible for reading the interrupt vector table (ivt) and transferri ng the address contained in the interrupt vector to the program counter. the inter- rupt vector is transferred from the program data bus into the program counter via a 24-bit wide multiplexer on the input of the program counter. the interrupt vector table (ivt) and alternate interrupt vector table (aivt) are pl aced near the beginning of program memory ( 0x000004 ). the ivt and aivt are shown in table 5-2. the interrupt controller is responsible for pre- processing the interrupts and processor exceptions prior to them being presented to the processor core. the peripheral interrupts an d traps are enabled, priori- tized and controlled using ce ntralized special function registers: ifs0<15:0>, ifs1<15:0>, ifs2<15:0> all interrupt request flags are maintained in these three registers. the flags are set by their respec- tive peripherals or extern al signals, and they are cleared via software. iec0<15:0>, iec1<15:0>, iec2<15:0> all interrupt enable contro l bits are maintained in these three registers. th ese control bits are used to individually enable interrupts from the peripherals or ex ternal signals. ipc0<15:0>... ipc10<7:0> the user assignable priority level associated with each of these 41 interrup ts is held centrally in these twelve registers. ipl<3:0> the current cpu priority level is explicitly stored in the ipl bits. ipl<3> is present in the corcon register, whereas ipl<2:0> are present in the status register (sr) in the processor core. intcon1<15:0>, intcon2<15:0> global interrupt control functions are derived from these two registers. intcon1 contains the con- trol and status flags for the processor exceptions. the intcon2 register controls the external interrupt request signal behavior and the use of the alternate vector table. all interrupt sources can be user assigned to one of 7 priority levels, 1 through 7, via the ipcx registers. each interrupt source is associated with an interrupt vector, as shown in table 5-2. levels 7 and 1 represent the highest and lowest maskable priorities, respectively. if the nstdis bit (intco n1<15>) is set, nesting of interrupts is prevented. thus, if an interrupt is currently being serviced, processing of a new interrupt is pre- vented even if the new interr upt is of higher priority than the one currently being serviced. certain interrupts have specialized control bits for fea- tures like edge or level trig gered interrupts, interrupt- on-change, etc. control of these features remains within the peripheral mo dule which generates the interrupt. the disi instruction can be used to disable the pro- cessing of interrupts of priorities 6 and lower for a cer- tain number of instructions, during which the disi bit (intcon2<14>) remains set. when an interrupt is serviced, the pc is loaded with the address stored in the vector location in program mem- ory that corresponds to the interrupt. there are 63 dif- ferent vectors within the ivt (refer to table 5-2). these vectors are contained in locations 0x000004 through 0x0000fe of program memory (refer to table 5-2). these locations contain 24-bi t addresses and in order to preserve robustness, an address error trap will take place should the pc attemp t to fetch any of these words during normal execution. this prevents execu- tion of random data as a re sult of accidentally decre- menting a pc into vector space, accidentally mapping a data space address into vector space, or the pc roll- ing over to 0x000000 after reaching the end of imple- mented program memory space. execution of a goto instruction to this vector sp ace will also generate an address error trap. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). note: interrupt flag bits ge t set when an interrupt condition occurs, regardless of the state of its corresponding enable bit. user soft- ware should ensure t he appropriate inter- rupt flag bits are clear prior to enabling an interrupt. note: assigning a priority level of ? 0 ? to an inter- rupt source is equiva lent to disabling that interrupt. note: the ipl bits become read only whenever the nstdis bit has been set to ? 1 ?.
dspic30f ds70083g-page 56 preliminary ? 2004 microchip technology inc. 5.1 interrupt priority the user assignable interrupt priority (ip<2:0>) bits for each individual interrupt so urce are located in the ls 3 bits of each nibble within the ipcx register(s). bit 3 of each nibble is not used and is read as a ? 0 ?. these bits define the priority level assig ned to a particular interrupt by the user. since more than one interrupt request source may be assigned to a specific user specified priority level, a means is provided to assign pr iority within a given level. this method is called ?nat ural order priority?. table 5-1 lists the interr upt numbers and interrupt sources for the dspic device and their associated vector numbers. the ability for the user to assign every interrupt to one of seven priority levels implies that the user can assign a very high overall priority level to an interrupt with a low natural order priority. for example, the plvd (low voltage detect) can be given a priority of 7. the int0 (external interrupt 0) may be assigned to priority level 1, thus giving it a very low effective priority. table 5-1: natural order priority note: the user selectable priority levels start at 0 as the lowest priori ty and level 7 as the highest priority. note 1: the natural order prio rity scheme has 0 as the highest priority and 53 as the lowest priority. 2: the natural order priority number is the same as the int number. int number vector number interrupt source highest natural order priority 0 8 int0 - external interrupt 0 1 9 ic1 - input capture 1 2 10 oc1 - output compare 1 3 11 t1 - timer 1 4 12 ic2 - input capture 2 5 13 oc2 - output compare 2 6 14 t2 - timer 2 7 15 t3 - timer 3 8 16 spi1 9 17 u1rx - uart1 receiver 10 18 u1tx - uart1 transmitter 11 19 adc - adc convert done 12 20 nvm - nvm write complete 13 21 si2c - i 2 c slave interrupt 14 22 mi2c - i 2 c master interrupt 15 23 input change interrupt 16 24 int1 - external interrupt 1 17 25 ic7 - input capture 7 18 26 ic8 - input capture 8 19 27 oc3 - output compare 3 20 28 oc4 - output compare 4 21 29 t4 - timer 4 22 30 t5 - timer 5 23 31 int2 - external interrupt 2 24 32 u2rx - uart2 receiver 25 33 u2tx - uart2 transmitter 26 34 spi2 27 35 c1 - combined irq for can1 28 36 ic3 - input capture 3 29 37 ic4 - input capture 4 30 38 ic5 - input capture 5 31 39 ic6 - input capture 6 32 40 oc5 - output compare 5 33 41 oc6 - output compare 6 34 42 oc7 - output compare 7 35 43 oc8 - output compare 8 36 44 int3 - external interrupt 3 37 45 int4 - external interrupt 4 38 46 c2 - combined irq for can2 39-40 47-48 reserved 41 49 dci - codec transfer done 42 50 lvd - low voltage detect 43-53 51-61 reserved lowest natural order priority
? 2004 microchip technology inc. preliminary ds70083g-page 57 dspic30f 5.2 reset sequence a reset is not a true except ion, because the interrupt controller is not involved in the reset process. the pro- cessor initializes its registers in response to a reset which forces the pc to ze ro. the processor then begins program execution at location 0x000000 . a goto instruction is stored in the first program memory loca- tion immediately followed by the address target for the goto instruction. the processor executes the goto to the specified address and th en begins operation at the specified target (start) address. 5.2.1 reset sources in addition to external reset and power-on reset (por), there are 6 sources of error conditions which ?trap? to the reset vector. watchdog time-out: the watchdog has timed out, indicating that the processor is no longer exec uting the correct flow of code. uninitialized w register trap: an attempt to use an unin itialized w register as an address pointer will cause a reset. illegal instruction trap: attempted execution of any unused opcodes will result in an illegal instruction trap. note that a fetch of an illegal instruct ion does not result in an illegal instruction trap if that instruction is flushed prior to execution due to a flow change. brown-out reset (bor): a momentary dip in th e power supply to the device has been detected which may result in malfunction. trap lockout: occurrence of multiple trap conditions simultaneously will cause a reset. 5.3 traps traps can be considered as non-maskable, non-stable interrupts, which adhere to a predefined priority, as shown in table 5-2. they are intended to provide the user a means to correct erroneous operation during debug and when operati ng within the application. note that many of these trap conditions can only be detected when they occur. consequently, the question- able instruction is allowed to complete prior to trap exception processing. if the user chooses to recover from the error, the result of the erroneous action that caused the trap may have to be corrected. there are 8 fixed priority leve ls for traps: level 8 through level 15, which implies that the ipl3 is always set during processing of a trap. if the user is not currently ex ecuting a trap, and he sets the ipl<3:0> bits to a value of ? 0111 ? (level 7), then all interrupts are disabled but traps can still be processed. 5.3.1 trap sources the following traps are prov ided with increasing prior- ity. however, since all traps can be nested, priority has little effect. math error trap: the math error trap exec utes under the following four circumstances: 1. should an attempt be made to divide by zero, the divide operatio n will be aborted on a cycle boundary and the trap taken. 2. if enabled, a math er ror trap will be taken when an arithmetic operation on either accumulator a or b causes an overflow from bit 31 and the accumulator guard bits are not utilized. 3. if enabled, a math er ror trap will be taken when an arithmetic operation on either accumulator a or b causes a catastrophic overflow from bit 39 and all saturation is disabled. 4. if the shift amount specified in a shift instruction is grea ter than the maximum allowed shift amount, a trap will occur. note: if the user does not intend to take correc- tive action in the event of a trap error con- dition, these vectors must be loaded with the address of a defa ult handler that sim- ply contains the reset instruction. if, on the other hand, one of the vectors contain- ing an invalid address is called, an address error trap is generated.
dspic30f ds70083g-page 58 preliminary ? 2004 microchip technology inc. address error trap: this trap is initiated when any of the following circumstances occurs: 1. a misaligned data word access is attempted. 2. a data fetch from and unimplemented data memory location is attempted. 3. a data fetch from an unimplemented pro- gram memory location is attempted. 4. an instruction fetch from vector space is attempted. 5. execution of a ? bra #litera l? instruction or a ? goto #literal ? instruction, where literal is an unimplemented program memory address. 6. executing instructions after modifying the pc to point to unimplemented program memory addresses. the pc may be modified by loading a value into the stack and executing a return instruction. stack error trap: this trap is initiated under the following conditions: 1. the stack pointer is loaded with a value which is greater than the (user program- mable) limit value written into the splim register (stack overflow). 2. the stack pointer is loaded with a value which is less than 0x0800 (simple stack underflow). oscillator fail trap: this trap is initiated if the external oscillator fails and operation becomes reliant on an internal rc backup. 5.3.2 hard and soft traps it is possible that multiple traps can become active within the same cycle (e.g., a misaligned word stack write to an overflowed address). in such a case, the fixed priority shown in figure 5-2 is implemented, which may require the user to check if other traps are pending in order to comp letely correct the fault. ?soft? traps include exceptions of priority level 8 through level 11, inclusive. the arithmetic error trap (level 11) falls into this category of trap s. soft traps can be treated like non-maskable sources of interrupt that adhere to the priority assigned by thei r position in the ivt. soft traps are processed like inte rrupts and require 2 cycles to be sampled and acknow ledged prior to exception processing. therefore, additional instructions may be executed before a soft trap is acknowledged. ?hard? traps include exceptions of priority level 12 through level 15, inclusive. the address error (level 12), stack error (level 13) an d oscillator error (level 14) traps fall into this category. like soft traps, hard traps can also be viewed as non- maskable sources of interrupt. the difference between hard traps and soft traps is that hard traps force the cpu to stop code execution after the instruction caus- ing the trap has completed. normal program execution flow will not resume until after the trap has been acknowledged and processed. if a higher priority trap oc curs while any lower priority trap is in progress, processing of the lower priority trap will be suspended and the hi gher priority trap will be acknowledged and processed. the lower priority trap will remain pending unti l processing of the higher priority trap completes. each hard trap that occurs must be acknowledged before code execution of any type may continue. if a lower priority hard trap occurs while a higher priority trap is pending, acknowledg ed, or is being processed, a hard trap conflict will occur. the conflict occurs because the lower priority trap cannot be acknowl- edged until processing for the higher priority trap completes. the device is automa tically reset in a hard trap conflict condition. the trapr status bit (rcon<15>) is set when the reset occurs so that the condition may be detected in software. in the case of a math error trap or oscillator failure trap, the condition that causes the trap to occur must be removed before the respective trap flag bit in the intcon1 register may be cleared. note: in the mac class of instructions, wherein the data space is split into x and y data space, unimplemented x space includes all of y space, and unimplemented y space includes all of x space.
? 2004 microchip technology inc. preliminary ds70083g-page 59 dspic30f 5.4 interrupt sequence all interrupt event flags are sampled in the beginning of each instruction cycle by t he ifsx registers. a pending interrupt request (irq) is indicated by the flag bit being equal to a ? 1 ? in an ifsx register . the irq will cause an interrupt to occur if the corr esponding bit in the interrupt enable (iecx) register is set. for the remainder of the instruction cycle, the prioriti es of all pending interrupt requests are evaluated. if there is a pending irq with a priority level greater than the current processor prio rity level in the ipl bits, the processor will be interrupted. the processor then stacks the current program counter and the low byte of the processor status register (srl), as shown in figure 5-1. the low byte of the status register contains the processor priority level at the time prior to the beginni ng of the interrupt cycle. the processor then loads the pr iority level for this inter- rupt into the status register. this action will disable all lower priority interrupts until the completion of the interrupt service routine. figure 5-1: interrupt stack frame the retfie (return from interrupt) instruction will unstack the program counte r and status registers to return the processor to its state prior to the interrupt sequence. figure 5-2: exception vectors 5.5 alternate vector table in program memory, the interrupt vector table (ivt) is followed by the alternate interrupt vector table (aivt), as shown in table 5-2. access to the alternate vector table is provided by the altivt bit in the intcon2 reg- ister. if the altivt bit is se t, all interrupt and exception processes will use the alternate vectors instead of the default vectors. the alternat e vectors are organized in the same manner as the default vectors. the aivt sup- ports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. this featur e also enables switching between applications for evaluation of different software algorithms at run time. if the aivt is not required, the program memory allo- cated to the aivt may be used for other purposes. aivt is not a protected section and may be freely programmed by the user. note 1: the user can always lower the priority level by writing a new value into sr. the interrupt service routine must clear the interrupt flag bits in the ifsx register before lowering th e processor interrupt priority, in order to avoid recursive interrupts. 2: the ipl3 bit (corcon<3>) is always clear when interrupts are being pro- cessed. it is set onl y during execution of traps. 0 15 w15 (before call ) w15 (after call ) stack grows towards higher address 0x0000 pc<15:0> srl ipl3 pc<22:16> pop : [--w15] push: [w15++] address error trap vector oscillator fail trap vector stack error trap vector reserved vector math error trap vector reserved oscillator fail trap vector address error trap vector reserved vector reserved vector interrupt 0 vector interrupt 1 vector ~ ~ ~ interrupt 52 vector interrupt 53 vector math error trap vector decreasing priority 0x000000 0x000014 reserved stack error trap vector reserved vector reserved vector interrupt 0 vector interrupt 1 vector ~ ~ ~ interrupt 52 vector interrupt 53 vector ivt aivt 0x000080 0x00007e 0x0000fe reserved 0x000094 reset - goto instruction reset - goto address 0x000002 reserved 0x000082 0x000084 0x000004 reserved vector
dspic30f ds70083g-page 60 preliminary ? 2004 microchip technology inc. 5.6 fast context saving a context saving option is available using shadow reg- isters. shadow registers are provided for the dc, n, ov, z and c bits in sr, an d the registers w0 through w3. the shadows are only one level deep. the shadow registers are accessible using the push.s and pop.s instructions only. when the processor vector s to an interrupt, the push.s instruction can be us ed to store the current value of the aforementioned registers into their respective shadow registers. if an isr of a certai n priority uses the push.s and pop.s instructions for fast context saving, then a higher priority isr should not include the same instruc- tions. users must save the key registers in software during a lower priority interr upt if the higher priority isr uses fast context saving. 5.7 external interrupt requests the interrupt controller supp orts up to five external interrupt request signals, in t0-int4. these inputs are edge sensitive; they require a low-to-high or a high-to- low transition to generate an interrupt request. the intcon2 register has five bits, int0ep-int4ep, that select the polarity of t he edge detection circuitry. 5.8 wake-up from sleep and idle the interrupt controller may be used to wake-up the processor from either sleep or idle modes, if sleep or idle mode is active when t he interrupt is generated. if an enabled interrupt request of sufficient priority is received by the interrupt co ntroller, then the standard interrupt request is presented to the processor. at the same time, the processor will wake-up from sleep or idle and begin execution of the interrupt service routine (isr) needed to process the interrupt request.
? 2004 microchip technology inc. preliminary ds70083g-page 61 dspic30f table 5-2: interrupt controller register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name adr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state intcon1 0080 nstdis ? ? ? ? ovate ovbte covte ? ? ? matherr addrerr stkerr oscfail ? 0000 0000 0000 0000 intcon2 0082 altivt ? ? ? ? ? ? ? ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 0000 0000 0000 ifs0 0084 cnif mi2cif si2cif nvmif adif u1txif u1rxi f spi1if t3if t2if oc2if ic2if t1if oc1if ic1if int0if 0000 0000 0000 0000 ifs1 0086 ic6if ic5if ic4if ic3if c1if spi2if u2txif u2 rxif int2if t5if t4if oc4if oc3if ic8if ic7if int1if 0000 0000 0000 0000 ifs2 0088 ? ? ? ? ? lvdif dciif ? ? c2if int4if int3if oc8if oc7if oc6if oc5if 0000 0000 0000 0000 iec0 008c cnie mi2cie si2cie nvmie adie u1txie u1r xie spi1ie t3ie t2ie oc2ie ic2ie t1ie oc1ie ic1ie int0ie 0000 0000 0000 0000 iec1 008e ic6ie ic5ie ic4ie ic3ie c1ie spi2ie u2txie u2 rxie int2ie t5ie t4ie oc4ie oc3ie ic8ie ic7ie int1ie 0000 0000 0000 0000 iec2 0090 ? ? ? ? ? lvdie dciie ? ? c2ie int4ie int3ie oc8ie oc7ie oc6ie oc5ie 0000 0000 0000 0000 ipc0 0094 ? t1ip<2:0> ? oc1ip<2:0> ? ic1ip<2:0> ? int0ip<2:0> 0100 0100 0100 0100 ipc1 0096 ? t31p<2:0> ? t2ip<2:0> ? oc2ip<2:0> ? ic2ip<2:0> 0100 0100 0100 0100 ipc2 0098 ? adip<2:0> ? u1txip<2:0> ? u1rxip<2:0> ? spi1ip<2:0> 0100 0100 0100 0100 ipc3 009a ? cnip<2:0> ? mi2cip<2:0> ? si2cip<2:0> ? nvmip<2:0> 0100 0100 0100 0100 ipc4 009c ? oc3ip<2:0> ? ic8ip<2:0> ? ic7ip<2:0> ? int1ip<2:0> 0100 0100 0100 0100 ipc5 009e ? int2ip<2:0> ? t5ip<2:0> ? t4ip<2:0> ? oc4ip<2:0> 0100 0100 0100 0100 ipc6 00a0 ? c1ip<2:0> ? spi2ip<2:0> ? u2txip<2:0> ? u2rxip<2:0> 0100 0100 0100 0100 ipc7 00a2 ? ic6ip<2:0> ? ic5ip<2:0> ? ic4ip<2:0> ? ic3ip<2:0> 0100 0100 0100 0100 ipc8 00a4 ? oc8ip<2:0> ? oc7ip<2:0> ? oc6ip<2:0> ? oc5ip<2:0> 0100 0100 0100 0100 ipc9 00a6 ? ? ? ? ? c2ip<2:0> ? int41ip<2:0> ? int3ip<2:0> 0000 0100 0100 0100 ipc10 00a8 ? ? ? ? ? lvdip<2:0> ? dciip<2:0> ? ? ? ? 0000 0100 0100 0000 legend: u = uninitialized bit
dspic30f ds70083g-page 62 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 63 dspic30f 6.0 flash program memory the dspic30f family of de vices contains internal pro- gram flash memory for executing user code. there are two methods by which the user can program this memory: 1. run-time self-programming (rtsp) 2. in-circuit serial programming? (icsp?) 6.1 in-circuit serial programming (icsp) dspic30f devices can be serially programmed while in the end application circuit. this is simply done with two lines for programming clock and programming data (which are named pgc and pgd respectively), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows cu stomers to manu- facture boards with unpr ogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 6.2 run-time self-programming (rtsp) rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user may erase and program 32 instructions (96 bytes) at a time. 6.3 table instruction operation summary the tblrdl and the tblwtl instructions are used to read or write to bits<15:0> of program memory. tblrdl and tblwtl can access program memory in word or byte mode. the tblrdh and tblwth instructions are used to read or write to bits<23:16> of program memory. tblrdh and tblwth can access program memory in word or byte mode. a 24-bit program memory address is formed using bits<7:0> of the tblpag register and the effective address (ea) from a w regist er specified in the table instruction, as shown in figure 6-1. figure 6-1: addressing for table and nvm registers note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). 0 program counter 24 bits nvmadru reg 8 bits 16 bits program using tblpag reg 8 bits working reg ea 16 bits using byte 24-bit ea 1/0 0 1/0 select table instruction nvmadr addressing counter using nvmadr reg ea user/configuration space select
dspic30f ds70083g-page 64 preliminary ? 2004 microchip technology inc. 6.4 rtsp operation the dspic30f flash program memory is organized into rows and panels. each row consists of 32 instruc- tions or 96 bytes. each panel consists of 128 rows or 4k x 24 instructions. rtsp al lows the user to erase and program one row (32 instruct ions) at a time. rtsp may be used to program multip le program memory panels, but the table pointer must be changed at each panel boundary. each panel of program memory contains write latches that hold 32 instructions of programming data. prior to the actual programming oper ation, the write data must be loaded into the panel wr ite latches. the data to be programmed into the panel is loaded in sequential order into the write latches: instruction 0, instruction 1, etc. the instruction words loaded must always be from a group of 32 boundary. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the write latches. programming is performed by setting the special bits in the nvmcon register. four tblwtl and four tblwth instructions are required to load the four instructions . to fully program a row of program memory, eight cycles of four tblwtl and four tblwth are required. if multiple panel programming is required, the table pointe r needs to be changed and the next set of multiple write latches written. all of the table write operat ions are single word writes (2 instruction cycles) because only the table latches are written. a total of 32 programming passes, each writing 4 instruction words, are required per row. the flash program memory is readable, writable, and erasable during normal operation over the entire v dd range. 6.5 control registers the four sfrs used to read and write the program flash memory are: nvmcon nvmadr nvmadru nvmkey 6.5.1 nvmcon register the nvmcon register contro ls which blocks are to be erased, which memory type is to be programmed and start of the programming cycle. 6.5.2 nvmadr register the nvmadr register is used to hold the lower two bytes of the effective address. the nvmadr register captures the ea<15:0> of the last table instruction that has been executed and selects the row to write. 6.5.3 nvmadru register the nvmadru register is used to hold the upper byte of the effective address. the nvmadru register cap- tures the ea<23:16> of the last table instruction that has been executed. 6.5.4 nvmkey register nvmkey is a write only reg ister that is used for write protection. to start a programming or an erase sequence, the user must consecutively write 0x55 and 0xaa to the nvmkey register. refer to section 6.6 for further details.
? 2004 microchip technology inc. preliminary ds70083g-page 65 dspic30f 6.6 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. a programming operation is nominally 2 msec in duration and the processor st alls (waits) until the oper- ation is finished. setting the wr bit (nvmcon<15>) starts the operation, and the wr bit is automatically cleared when the oper ation is finished. 6.6.1 programming algorithm for program flash the user can erase one row of program flash memory at a time. the user can program one block (4 instruction words) of fl ash memory at a time. the general process is: 1. read one row of program flash (32 instruction words) and store into data ram as a data ?image?. 2. update the data image with the desired new data. 3. erase program flash row. a) setup nvmcon register for multi-word, program flash, erase, and set wren bit. b) write address of row to be erased into nvmadru/nvmadr. c) write ?55? to nvmkey. d) write ?aa? to nvmkey. e) set the wr bit. this will begin erase cycle. f) cpu will stall for the duration of the erase cycle. g) the wr bit is clear ed when erase cycle ends. 4. write 32 instruction words of data from data ram into the program flash write latches. 5. program 32 instruction words into program flash. a) setup nvmcon register for multi-word, program flash, program, and set wren bit. b) write ?55? to nvmkey. c) write ?aa? to nvmkey. d) set the wr bit. this will begin program cycle. e) cpu will stall for duration of the program cycle. f) the wr bit is cleared by the hardware when program cycle ends. 6. repeat steps 1 through 5 as needed to program desired amount of pr ogram flash memory. 6.6.2 erasing a row of program memory example 6-1 shows a code sequence that can be used to erase a row (32 instruct ions) of program memory. example 6-1: erasing a row of program memory ; setup nvmcon for erase operation, multi word write ; program memory selected, and writes enabled mov #0x4041,w0 ; mov w0 , nvmcon ; init nvmcon sfr ; init pointer to ro w to be erased mov #tblpage(prog_addr),w0 ; mov w0 , nvmadru ; initialize pm page boundary sfr mov #tbloffset(prog_addr),w0 ; in tialize in-page ea[15:0] pointer mov w0, nvmadr ; initialize nvmadr sfr disi #5 ; block all inter rupts with priority <7 for ; next 5 instructions mov #0x55,w0 mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; start the erase sequence nop ; insert two n ops after the erase nop ; command is asserted
dspic30f ds70083g-page 66 preliminary ? 2004 microchip technology inc. 6.6.3 loading write latches example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. four tblwtl and four tblwth instructions are needed to load the write latches select ed by the table pointer. example 6-2: loading write latches 6.6.4 initiating the programming sequence for protection, the write in itiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the pr ogramming command has been executed, the user must wa it for the programming time until programming is complete . the two instructions fol- lowing the start of the programming sequence should be nop s. example 6-3: initiating a programming sequence ; set up a pointer to the first program memory loca tion to be written ; program memory selec ted, and writes enabled mov #0x0000,w0 ; mov w0 , tblpag ; initialize pm page boundary sfr mov #0x6000,w0 ; an exam ple program memory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low_word_0,w2 ; mov #high_byte_0,w3 ; tblwtl w2 , [w0] ; write pm low word into program latch tblwth w3 , [w0++] ; write pm high byte into program latch ; 1st_program_word mov #low_word_1,w2 ; mov #high_byte_1,w3 ; tblwtl w2 , [w0] ; write pm low word into program latch tblwth w3 , [w0++] ; write pm high byte into program latch ; 2nd_program_word mov #low_word_2,w2 ; mov #high_byte_2,w3 ; tblwtl w2 , [w0] ; write pm low word into program latch tblwth w3 , [w0++] ; write pm high byte into program latch ; 31st_program_word mov #low_word_3,w2 ; mov #high_byte_3,w3 ; tblwtl w2 , [w0] ; write pm low word into program latch tblwth w3 , [w0++] ; write pm high byte into program latch note: in example 6-2, the contents of th e upper byte of w3 has no effect. disi #5 ; block all interrupts with priority <7 for ; next 5 instructions mov #0x55,w0 ; mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; start the erase sequence nop ; insert two no ps after the erase nop ; command is asserted
? 2004 microchip technology inc. preliminary ds70083g-page 67 dspic30f table 6-1: nvm register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. file name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr ? ? ? ? twri ? progop<6:0> 0000 0000 0000 0000 nvmadr 0762 nvmadr<15:0> uuuu uuuu uuuu uuuu nvmadru 0764 ? ? ? ? ? ? ? ? nvmadr<23:16> 0000 0000 uuuu uuuu nvmkey 0766 ? ? ? ? ? ? ? ? key<7:0> 0000 0000 0000 0000 legend: u = uninitialized bit
dspic30f ds70083g-page 68 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 69 dspic30f 7.0 data eeprom memory the data eeprom memory is readable and writable during normal operation over the entire v dd range. the data eeprom memory is directly mapped in the program memory address space. the four sfrs used to read and write the program flash memory are used to access data eeprom memory, as well. as described in section 6.5, these registers are: nvmcon nvmadr nvmadru nvmkey the eeprom data memory allows read and write of single words and 16-word blocks. when interfacing to data memory, nvmadr in conjunction with the nvmadru register are used to address the eeprom location being accessed. tblrdl and tblwtl instructions are used to read and write data eeprom. the dspic30f devices have up to 8 kbytes (4k words) of data eeprom with an address range from 0x7ff000 to 0x7ffffe . a word write operation should be preceded by an erase of the corresponding memory location(s). the write typ- ically requires 2 ms to comp lete but the write time will vary with voltage and temperature. a program or erase oper ation on the data eeprom does not stop the instruction flow. th e user is respon- sible for waiting for the app ropriate duration of time before initiating another data eeprom write/erase operation. attempting to re ad the data eeprom while a programming or erase operat ion is in progress results in unspecified data. control bit wr initiates wr ite operations similar to pro- gram flash writes. this bit cannot be cleared, only set, in software. they are cleared in hardware at the com- pletion of the write operation. the inability to clear the wr bit in software prevents the accidental or premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset or a wdt time-out reset during normal opera- tion. in these situations, following reset, the user can check the wrerr bit and re write the location. the address register nvma dr remains unchanged. 7.1 reading the data eeprom a tblrd instruction reads a word at the current pro- gram word address. this example uses w0 as a pointer to data eeprom. the result is placed in register w4 as shown in example 7-1. example 7-1: data eeprom read note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030). note: interrupt flag bit nvmif in the ifs0 regis- ter is set when write is complete. it must be cleared in software. mov #low_addr_word,w0 ; init pointer mov #high_addr_word,w1 mov w1 , tblpag tblrdl [ w0 ], w4 ; read data eeprom
dspic30f ds70083g-page 70 preliminary ? 2004 microchip technology inc. 7.2 erasing data eeprom 7.2.1 erasing a block of data eeprom in order to erase a block of data eeprom, the nvmadru and nvmadr register s must initially point to the block of memory to be erased. configure nvmcon for erasing a block of data eeprom, and set the erase and wren bits in the nvmcon register. setting the wr bit initiates the erase as shown in example 7-2. example 7-2: data eeprom block erase 7.2.2 erasing a word of data eeprom the tblpag and nvmadr registers must point to the block. select erase a block of data flash, and set the erase and wren bits in the nvmcon register. set- ting the wr bit initiates the erase as shown in example 7-3. example 7-3: data eeprom word erase ; select data eeprom blo ck, erase, wren bits mov #4045,w0 mov w0 , nvmcon ; init ialize nvmcon sfr ; start erase cycle by setting wr after writing key sequence disi #5 ; block all interru pts with priority <7 for ; next 5 instructions mov #0x55,w0 ; mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; init iate erase sequence nop nop ; erase cycle will complete in 2ms. cpu is not stalled for the data erase cycle ; user can poll wr bi t, use nvmif or timer irq to determine erasure complete ; select data eeprom word, erase, wren bits mov #4044,w0 mov w0 , nvmcon ; start erase cycle by setting wr after writing key sequence disi #5 ; block all interr upts with priority <7 for ; next 5 instructions mov #0x55,w0 ; mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 ; mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; initiate erase sequence nop nop ; erase cycle will complet e in 2ms. cpu is not stalle d for the data erase cycle ; user can poll wr bit, us e nvmif or timer irq to determine erasure complete
? 2004 microchip technology inc. preliminary ds70083g-page 71 dspic30f 7.3 writing to the data eeprom to write an eeprom data location, the following sequence must be followed: 1. erase data eeprom word. a) select word, data eeprom erase, and set wren bit in nvmcon register. b) write address of word to be erased into nvmadr. c) enable nvm interrupt (optional). d) write ?55? to nvmkey. e) write ?aa? to nvmkey. f) set the wr bit. this will begin erase cycle. g) either poll nvmif bi t or wait for nvmif interrupt. h) the wr bit is cleared when the erase cycle ends. 2. write data word into data eeprom write latches. 3. program 1 data word into data eeprom. a) select word, data eeprom program, and set wren bit in nvmcon register. b) enable nvm write done interrupt (optional). c) write ?55? to nvmkey. d) write ?aa? to nvmkey. e) set the wr bit. this will begin program cycle. f) either poll nvmif bit or wait for nvm interrupt. g) the wr bit is cleared when the write cycle ends. the write will not initiate if the above sequence is not exactly followed (write 0x55 to nvmkey, write 0xaa to nvmcon, then set wr bit) fo r each word. it is strongly recommended that interrupt s be disabled during this code segment. additionally, the wren bit in nvmcon must be set to enable writes. this mechanism prevents accidental writes to data eeprom due to unexpected code exe- cution. the wren bit should be kept clear at all times except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequen ce has been initiated, clearing the wren bit will not affect the current write cycle. the wr bit will be inhibited from bei ng set unless the wren bit is set. the wren bit must be set on a previous instruc- tion. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared in hardware and the non-volatile memory write complete interrupt fl ag bit (nvmif) is set. the user may either enable this interrupt or poll this bit. nvmif must be cleared by software. 7.3.1 writing a word of data eeprom once the user has erased t he word to be programmed, then a table write instruction is used to write one write latch, as shown in example 7-4. example 7-4: data eeprom word write ; point to data memory mov #low_addr_word,w0 ; init pointer mov #high_addr_word,w1 mov w1 , tblpag mov #low(word),w2 ; get data tblwtl w2 , [ w0] ; write data ; the nvmadr captures last table access address ; select data ee prom for 1 word op mov #0x4004,w0 mov w0 , nvmcon ; operate key to allow write operation disi #5 ; block all interrupts with priority <7 for ; next 5 instructions mov #0x55,w0 mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; init iate program sequence nop nop ; write cycle will complete in 2ms. cpu is not st alled for the data write cycle ; user can poll wr bit, us e nvmif or timer irq to determine write complete
dspic30f ds70083g-page 72 preliminary ? 2004 microchip technology inc. 7.3.2 writing a block of data eeprom to write a block of data e eprom, write to all sixteen latches first, then set the nvmcon register and program the block. example 7-5: data eeprom block write mov #low_addr_wor d,w0 ; init pointer mov #high_addr_word,w1 mov w1 , tblpag mov #data1,w2 ; get 1st data tblwtl w2 , [ w0]++ ; write data mov #data2,w2 ; get 2nd data tblwtl w2 , [ w0]++ ; write data mov #data3,w2 ; get 3rd data tblwtl w2 , [ w0]++ ; write data mov #data4,w2 ; get 4th data tblwtl w2 , [ w0]++ ; write data mov #data5,w2 ; get 5th data tblwtl w2 , [ w0]++ ; write data mov #data6,w2 ; get 6th data tblwtl w2 , [ w0]++ ; write data mov #data7,w2 ; get 7th data tblwtl w2 , [ w0]++ ; write data mov #data8,w2 ; get 8th data tblwtl w2 , [ w0]++ ; write data mov #data9,w2 ; get 9th data tblwtl w2 , [ w0]++ ; write data mov #data10,w 2 ; get 10th data tblwtl w2 , [ w0]++ ; write data mov #data11,w 2 ; get 11th data tblwtl w2 , [ w0]++ ; write data mov #data12,w 2 ; get 12th data tblwtl w2 , [ w0]++ ; write data mov #data13,w 2 ; get 13th data tblwtl w2 , [ w0]++ ; write data mov #data14,w 2 ; get 14th data tblwtl w2 , [ w0]++ ; write data mov #data15,w 2 ; get 15th data tblwtl w2 , [ w0]++ ; write data mov #data16,w 2 ; get 16th data tblwtl w2 , [ w0]++ ; write data. t he nvmadr captures last table access address. mov #0x400a,w0 ; select data eeprom f or multi word op mov w0 , nvmcon ; operate key to allow program operation disi #5 ; block all interrupts with priority <7 for ; next 5 instructions mov #0x55,w0 mov w0 , nvmkey ; write the 0x55 key mov #0xaa,w1 mov w1 , nvmkey ; write the 0xaa key bset nvmcon,#wr ; start write cycle nop nop
? 2004 microchip technology inc. preliminary ds70083g-page 73 dspic30f 7.4 write verify depending on the applicati on, good programming practice may dictat e that the value written to the mem- ory should be verified against the original value. this should be used in applicat ions where excessive writes can stress bits near the specification limit. 7.5 protection against spurious write there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, the wren bit is cleared; also, the power-up timer prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidenta l write during brown-out, power glitch, or software malfunction.
dspic30f ds70083g-page 74 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 75 dspic30f 8.0 i/o ports all of the device pins (except v dd , v ss , mclr , and osc1/clki) are shared between the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 8.1 parallel i/o (pio) ports when a peripheral is enabl ed and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pi n is disabled. the i/o pin may be read but the output driver for the parallel port bit will be disabled. if a periph eral is enabled but the peripheral is not actively driving a pin, that pin may be driven by a port. all port pins have three registers directly associated with the operation of the po rt pin. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a ? 1 ?, then the pin is an input. all port pins ar e defined as inputs after a reset. reads from the latch (latx), read the latch. writes to the latch, write the latch (latx). reads from the port (portx), read the port pins and writes to the port pins, write the latch (latx). any bit and its associated data and control registers that are not valid for a part icular device will be dis- abled. that means the corr esponding latx and trisx registers and the port pin will read as zeros. when a pin is shared with an other peripheral or func- tion that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. an example is the int4 pin. the format of the registers for porta are shown in ta b l e 8 - 1 . the trisa (data direction control) register controls the direction of the ra<7:0> pins, as well as the intx pins and the v ref pins. the lata register supplies data to the outputs and is readable/writable. reading the porta register yields the state of the input pins, while writing the porta reg ister modifies the contents of the lata register. a parallel i/o (pio) port that shares a pin with a periph- eral is, in general, subservie nt to the peripheral. the peripheral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pad cell. figure 8-2 shows how ports are shared with other peripherals and the associated i/o cell (pad) to which they are connected. table 8-2 through table 8-6 show the formats of the registers for the shared ports, portb through portg. figure 8-1: block diagram of a dedicated port structure note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: the actual bits in use vary between devices. q d ck wr lat + tris latch i/o pad wr port data bus q d ck data latch read lat read port read tris wr tris i/o cell dedicated port module
dspic30f ds70083g-page 76 preliminary ? 2004 microchip technology inc. figure 8-2: block diagram of a shared port structure 8.2 configuring analog port pins the use of the adpcfg and tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs mu st have their correspond- ing tris bit set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. when reading the port regist er, all pins configured as analog input channels will read as cleared (a low level). pins configured as digital inputs will not convert an analog input. analog levels on any pin that is defined as a digital input (including the anx pins) may cause the input buffer to consume current that exceeds the device specifications. 8.2.1 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be a nop . example 8-1: port write/read example q d ck wr lat + tris latch i/o pad wr port data bus q d ck data latch read lat read port read tris 1 0 1 0 wr tris peripheral output data output enable peripheral input data i/o cell peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable mov 0xff00, w0 ; confi gure portb<15:8> ; as inputs mov w0, trisb ; and portb<7:0> as outputs nop ; additional instruction cylcle btss portb, #13 ; bit te st rb13 and skip if set
? 2004 microchip technology inc. preliminary ds70083g-page 77 dspic30f table 8-1: porta register map table 8-2: portb register map table 8-3: portc register map table 8-4: portd register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 b it 2 bit 1 bit 0 reset state trisa 02c0 trisa15 trisa14 trisa13 trisa12 ? trisa10 trisa9 ? trisa7 trisa6 ? ? ? ? ? ? 1111 0110 1100 0000 porta 02c2 ra15 ra14 ra13 ra12 ? ra10 ra9 ? ra7 ra6 ? ? ? ? ? ? 0000 0000 0000 0000 lata 02c4 lata15 lata14 lata13 lata12 ? lata10 lata9 ? lata7 lata6 ? ? ? ? ? ? 0000 0000 0000 0000 legend: u = uninitialized bit sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 b it 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisb 02c6 trisb15 trisb14 trisb13 trisb12 tr isb11 trisb10 trisb9 trisb8 trisb7 trisb6 t risb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 portb 02c8 rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 0000 0000 0000 0000 latb 02cb latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 0000 0000 0000 0000 legend: u = uninitialized bit sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 b it 2 bit 1 bit 0 reset state trisc 02cc trisc15 trisc14 trisc13 ? ? ? ? ? ? ? ? trisc4 trisc3 trisc2 trisc1 ? 1110 0000 0001 1110 portc 02ce rc15 rc14 rc13 ? ? ? ? ? ? ? ? rc4 rc3 rc2 rc1 ? 0000 0000 0000 0000 latc 02d0 latc15 latc14 latc13 ? ? ? ? ? ? ? ? latc4 latc3 latc2 latc1 ? 0000 0000 0000 0000 legend: u = uninitialized bit sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisd 02d2 trisd15 trisd14 trisd13 trisd12 trisd11 trisd10 trisd 9 trisd8 trisd7 trisd6 trisd5 tri sd4 trisd3 trisd2 trisd1 trisd0 1111 1111 1111 1111 portd 02d4 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 0000 0000 0000 0000 latd 02d6 latd15 latd14 latd13 latd12 latd11 latd10 latd9 latd8 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 0000 0000 0000 0000 legend: u = uninitialized bit
dspic30f ds70083g-page 78 preliminary ? 2004 microchip technology inc. table 8-5: portf register map table 8-6: portg register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bi t 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisf 02de ? ? ? ? ? ? ? trisf8 trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 0000 0001 1111 1111 portf 02e0 ? ? ? ? ? ? ? rf8 rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 0000 0000 0000 0000 latf 02e2 ? ? ? ? ? ? ? latf8 latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 0000 0000 0000 0000 legend: u = uninitialized bit sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state trisg 02e4 trisg15 tr isg14 trisg13 trisg12 ? ? trisg9 trisg8 trisg7 trisg6 ? ? trisg3 trisg2 trisg1 trisg0 1111 0011 1100 1111 portg 02e6 rg15 rg14 rg13 rg12 ? ? rg9 rg8 rg7 rg6 ? ? rg3 rg2 rg1 rg0 0000 0000 0000 0000 latg 02e8 latg15 latg14 latg13 latg12 ? ? latg9 latg8 latg7 latg6 ? ? latg3 latg2 latg1 latg0 0000 0000 0000 0000 legend: u = uninitialized bit
? 2004 microchip technology inc. preliminary ds70083g-page 79 dspic30f 8.3 input change notification module the input change notificati on module provides the dspic30f devices the ability to generate interrupt requests to the processor, in response to a change of state on selected input pins . this module is capable of detecting input change of states even in sleep mode, when the clocks are disabled. there are up to 24 exter- nal signals (cn0 through cn2 3) that may be selected (enabled) for generating an interrupt request on a change of state. table 8-7: input change notification register map (bits 15-8) table 8-8: input change notification register map (bits 7-0) note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reset state cnen1 00c0 cn15ie cn14ie cn13ie cn12ie cn11ie cn10ie cn9ie cn8ie 0000 0000 0000 0000 cnen2 00c2 ? ? ? ? ? ? ? ? 0000 0000 0000 0000 cnpu1 00c4 cn15pue cn14pue cn13pue cn12pue cn11pue cn10pue cn9pue cn8pue 0000 0000 0000 0000 cnpu2 00c6 ? ? ? ? ? ? ? ? 0000 0000 0000 0000 legend: u = uninitialized bit sfr name addr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state cnen1 00c0 cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 0000 0000 0000 cnen2 00c2 cn23ie cn22ie cn21ie cn20ie cn19ie cn18ie cn17ie cn16ie 0000 0000 0000 0000 cnpu1 00c4 cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 0000 0000 0000 cnpu2 00c6 cn23pue cn22pue cn21pue cn20pue cn19pue cn18pue cn17pue cn16pue 0000 0000 0000 0000 legend: u = uninitialized bit
dspic30f ds70083g-page 80 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 81 dspic30f 9.0 timer1 module this section describes th e 16-bit general purpose (gp) timer1 module and associated operational modes. figure 9-1 depicts t he simplified block diagram of the 16-bit timer1 module. the following sections prov ide a detailed description including setup and control re gisters, along with asso- ciated block diagrams for the operational modes of the timers. the timer1 module is a 16-bit timer which can serve as the time counter for the real-time clock, or operate as a free-running interval timer/counter. the 16-bit timer has the following modes: 16-bit timer 16-bit synchronous counter 16-bit asynchronous counter further, the following operational characteristics are supported: timer gate operation selectable prescaler settings timer operation during cpu idle and sleep modes interrupt on 16-bit period register match or falling edge of external gate signal these operating modes are determined by setting the appropriate bit(s) in the 16-bit sfr, t1con. figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit timer mode: in the 16-bit timer mode, the timer increments on every instruction cycle up to a match value preloaded into the period register pr1, then resets to ? 0 ? and continues to count. when the cpu goes into the idle mode, the timer will stop incrementing unless the tsidl (t1con<13>) bit = 0 . if tsidl = 1 , the timer module logic will resume the incrementing sequence upon termination of the cpu idle mode. 16-bit synchronous counter mode: in the 16-bit synchronous counter mode, the timer increments on the rising edge of the ap plied external clock signal which is synchronized with the internal phase clocks. the timer counts up to a ma tch value preloaded in pr1, then resets to ? 0 ? and continues. when the cpu goes into the idle mode, the timer will stop incrementing unless the respective tsidl bit = 0 . if tsidl = 1 , the timer module logic will resume the incrementing sequence upon termination of the cpu idle mode. 16-bit asynchronous counter mode: in the 16-bit asynchronous counter mode, the timer increments on every rising edge of the a pplied external clock signal. the timer counts up to a ma tch value preloaded in pr1, then resets to ? 0 ? and continues. when the timer is configur ed for the asynchronous mode of operation and t he cpu goes into the idle mode, the timer will stop incrementing if tsidl = 1 . figure 9-1: 16-bit timer1 module block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). ton sync sosci sosco/ pr1 t1if equal comparator x 16 tmr1 reset lposcen event flag 1 0 tsync q q d ck tgate tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 t1ck tcs 1 x 0 1 tgate 0 0 gate sync
dspic30f ds70083g-page 82 preliminary ? 2004 microchip technology inc. 9.1 timer gate operation the 16-bit timer can be plac ed in the gated time accu- mulation mode. this mode allows the internal t cy to increment the respective time r when the gate input sig- nal (t1ck pin) is asserted high. control bit tgate (t1con<6>) must be set to enable this mode. the timer must be enabled (ton = 1 ) and the timer clock source set to internal (tcs = 0 ). when the cpu goes into the idle mode, the timer will stop incrementing unless tsidl = 0 . if tsidl = 1 , the timer will resume the incrementing sequence upon termination of the cpu idle mode. 9.2 timer prescaler the input clock (f osc /4 or external clock) to the 16-bit timer has a prescale option of 1:1, 1:8, 1:64 and 1:256, selected by control bits tckps<1:0> (t1con<5:4>). the prescaler counter is cleared when any of the following occurs: a write to the tmr1 register clearing of the ton bit (t1con<15>) device reset, such as por and bor however, if the time r is disabled (ton = 0 ), then the timer prescaler cannot be reset since the prescaler clock is halted. tmr1 is not cleared when t1con is written. it is cleared by writing to the tmr1 register. 9.3 timer operation during sleep mode during cpu sleep mode, the timer will operate if: the timer module is enabled (ton = 1 ) and the timer clock source is selected as external (tcs = 1 ) and the tsync bit (t1con<2>) is asserted to a logic ? 0 ? which defines the external clock source as asynchronous. when all three conditions ar e true, the timer will con- tinue to count up to the pe riod register and be reset to 0x0000 . when a match between the ti mer and the period regis- ter occurs, an interrupt can be generated if the respective timer interrup t enable bit is asserted. 9.4 timer interrupt the 16-bit timer has the ability to generate an interrupt on period match. when the timer count matches the period register, the t1if bit is asse rted and an interrupt will be generated if enabled. the t1if bit must be cleared in software. the timer interrupt fl ag, t1if, is located in the ifs0 control register in the interrupt controller. when the gated time accum ulation mode is enabled, an interrupt will also be g enerated on the falling edge of the gate signal (at the end of the accumulation cycle). enabling an interrupt is ac complished via the respec- tive timer interrupt enable bit, t1ie. the timer interrupt enable bit is located in the ie c0 control register in the interrupt controller. 9.5 real-time clock timer1, when operating in real-time clock (rtc) mode, provides time of day and event time-stamping capabilities. key operational features of the rtc are: operation from 32 khz lp oscillator 8-bit prescaler low power real-time clock interrupts these operating modes are determined by setting the appropriate bit(s) in the t1con control register. figure 9-2: recommended components for timer1 lp oscillator rtc sosci sosco r c1 c2 dspic30fxxxx 32.768 khz xtal c1 = c2 = 18 pf; r = 100k
? 2004 microchip technology inc. preliminary ds70083g-page 83 dspic30f 9.5.1 rtc oscillator operation when the ton = 1 , tcs = 1 and tgate = 0 , the timer increments on the rising edg e of the 32 khz lp oscilla- tor output signal, up to the va lue specified in the period register and is then reset to ? 0 ?. the tsync bit must be asserted to a logic ? 0 ? (asynchronous mode) for correct operation. enabling lposcen (osccon< 1>) will disable the normal timer and counter modes and enable a timer carry-out wake-up event. when the cpu enters slee p mode, the rtc will con- tinue to operate provided the 32 khz external crystal oscillator is active and t he control bits have not been changed. the tsidl bit should be cleared to ? 0 ? in order for rtc to continue operation in idle mode. 9.5.2 rtc interrupts when an interrupt event occur s, the respective interrupt flag, t1if, is asserted and an interrupt will be generated if enabled. the t1if bit must be cleared in software. the respective timer interrupt flag, t1if, is located in the ifs0 status register in the interrupt controller. enabling an interrupt is ac complished via the respec- tive timer interrupt enable bi t, t1ie. the timer interrupt enable bit is located in the ie c0 control register in the interrupt controller.
dspic30f ds70083g-page 84 preliminary ? 2004 microchip technology inc. table 9-1: timer1 register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state tmr1 0100 timer1 register uuuu uuuu uuuu uuuu pr1 0102 period register 1 1111 1111 1111 1111 t1con 0104 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? tsync tcs ? 0000 0000 0000 0000 legend: u = uninitialized bit
? 2004 microchip technology inc. preliminary ds70083g-page 85 dspic30f 10.0 timer2/3 module this section describes th e 32-bit general purpose (gp) timer module (timer2/3) and associated opera- tional modes. figure 10-1 de picts the simplified block diagram of the 32-bit ti mer2/3 module. figure 10-2 and figure 10-3 show timer2/3 configured as two independent 16-bit time rs, timer2 and timer3, respectively. the timer2/3 module is a 32-bit timer (which can be configured as two 16-bit timers) with selectable operating modes. these timers are utilized by other peripheral modules, such as: input capture output compare/simple pwm the following sections prov ide a detailed description, including setup and control re gisters, along with asso- ciated block diagrams for the operational modes of the timers. the 32-bit timer has the following modes: two independent 16-bit timers (timer2 and timer3) with all 16-bit operating modes (except asynchronous counter mode) single 32-bit timer operation single 32-bit synchronous counter further, the following operational characteristics are supported: adc event trigger timer gate operation selectable prescaler settings timer operation during idle and sleep modes interrupt on a 32-bit period register match these operating modes are de termined by setting the appropriate bit(s) in th e 16-bit t2con and t3con sfrs. for 32-bit timer/counter o peration, timer2 is the ls word and timer3 is the ms wo rd of the 32-bit timer. 16-bit timer mode: in the 16-bit mode, timer2 and timer3 can be configured as two independent 16-bit timers. each timer can be set up in either 16-bit timer mode or 16-bit synchronous counter mode. see section 9.0, timer1 module for details on these two operating modes. the only functional differ ence between timer2 and timer3 is that timer2 prov ides synchronization of the clock prescaler output. this is useful for high frequency external clock inputs. 32-bit timer mode: in the 32-bit timer mode, the timer increments on every instruction cycle, up to a match value preloaded into th e combined 32-bit period register pr3/pr2, then resets to ? 0 ? and continues to count. for synchronous 32-bit reads of the timer2/timer3 pair, reading the ls word (tmr2 register) will cause the ms word to be read and latched into a 16-bit holding register, termed tmr3hld. for synchronous 32-bit writes, the holding register (tmr3hld) must first be written to. when followed by a write to the tmr2 register, the contents of tmr3hld will be transferred and latched into the msb of the 32-bit timer (tmr3). 32-bit synchronous counter mode: in the 32-bit synchronous counter mode, the timer increments on the rising edge of the ap plied external clock signal which is synchronized with the internal phase clocks. the timer counts up to a ma tch value preloaded in the combined 32-bit period regist er pr3/pr2, then resets to ? 0 ? and continues. when the timer is configured for the synchronous counter mode of operation and the cpu goes into the idle mode, the timer will stop incrementing unless the tsidl (t2con<13>) bit = 0 . if tsidl = 1 , the timer module logic will resume the incrementing sequence upon termination of the cpu idle mode. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: for 32-bit timer operation, t3con control bits are ignored. only t2con control bits are used for setup and control. timer2 clock and gate inputs are utilized for the 32-bit timer module bu t an interrupt is gen- erated with the timer3 interrupt flag (t3if) and the interrupt is enabled with the timer3 interrupt enable bit (t3ie). note: in some devices, one or more of the t x ck pins may be absent. therefore, for such timers, the following modes should not be used: 1. tcs = 1 (16-bit counter) 2. tcs = 0, tgate = 1 (gated time accumulation.
dspic30f ds70083g-page 86 preliminary ? 2004 microchip technology inc. figure 10-1: 32-bit timer2/3 block diagram tmr3 tmr2 t3if equal comparator x 32 pr3 pr2 reset lsb msb event flag note: timer configuration bit t32 (t2con<3>) must be set to ? 1 ? for a 32-bit timer/counter operation. all control bits are respective to the t2con register. data bus<15:0> read tmr2 write tmr2 16 16 16 q q d ck tgate (t2con<6>) (t2con<6>) tgate 0 1 ton tckps<1:0> 2 t cy tcs 1 x 0 1 tgate 0 0 gate t2ck sync adc event trigger sync tmr3hld prescaler 1, 8, 64, 256
? 2004 microchip technology inc. preliminary ds70083g-page 87 dspic30f figure 10-2: 16-bit timer2 block diagram figure 10-3: 16-bit timer3 block diagram ton sync pr2 t2if equal comparator x 16 tmr2 reset event flag tgate tckps<1:0> 2 tgate t cy 1 0 tcs 1 x 0 1 tgate 0 0 gate t2ck sync prescaler 1, 8, 64, 256 q q d ck ton pr3 t3if equal comparator x 16 tmr3 reset event flag tgate tckps<1:0> 2 tgate t cy 1 0 tcs 1 x 0 1 tgate 0 0 t3ck adc event trigger sync q q d ck prescaler 1, 8, 64, 256
dspic30f ds70083g-page 88 preliminary ? 2004 microchip technology inc. 10.1 timer gate operation the 32-bit timer can be plac ed in the gated time accu- mulation mode. this mode allows the internal t cy to increment the respective time r when the gate input sig- nal (t2ck pin) is asserted high. control bit tgate (t2con<6>) must be set to enable this mode. when in this mode, timer2 is the orig inating clock source. the tgate setting is ignored fo r timer3. the timer must be enabled (ton = 1 ) and the timer clock source set to internal (tcs = 0 ). the falling edge of the exte rnal signal terminates the count operation but does not reset the timer. the user must reset the timer in order to start counting from zero. 10.2 adc event trigger when a match occurs betw een the 32-bit timer (tmr3/ tmr2) and the 32-bit combin ed period register (pr3/ pr2), or between the 16-bit timer (tmr3) and the 16- bit period register (pr3), a special adc trigger event signal is generated by timer3. 10.3 timer prescaler the input clock (f osc /4 or external clock) to the timer has a prescale option of 1:1, 1:8, 1:64, and 1:256, selected by control bits tckps<1:0> (t2con<5:4> and t3con<5:4>). for the 32 -bit timer operation, the originating clock source is timer2. the prescaler oper- ation for timer3 is not applicable in this mode. the prescaler counter is cleared when any of the following occurs: a write to the tmr2/tmr3 register clearing either of the ton (t2con<15> or t3con<15>) bits to ? 0 ? device reset, such as por and bor however, if the time r is disabled (ton = 0 ), then the timer 2 prescaler cannot be reset since the prescaler clock is halted. tmr2/tmr3 is not cleared when t2con/t3con is written. 10.4 timer operation during sleep mode during cpu sleep mode, the timer will not operate because the internal clocks are disabled. 10.5 timer interrupt the 32-bit timer module can generate an interrupt on period match or on the falli ng edge of the external gate signal. when the 32-bit timer count matches the respective 32-bit period reg ister, or the falling edge of the external ?gate? signal is detected, the t3if bit (ifs0<7>) is asserted and an interrupt will be gener- ated if enabled. in this mode, the t3if interrupt flag is used as the source of the interrupt. the t3if bit must be cleared in software. enabling an interrupt is accomplished via the respective timer interrupt enable bit, t3ie (iec0<7>).
? 2004 microchip technology inc. preliminary ds70083g-page 89 dspic30f table 10-1: timer2/3 register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state tmr2 0106 timer2 register uuuu uuuu uuuu uuuu tmr3hld 0108 timer3 holding register (f or 32-bit timer operations only) uuuu uuuu uuuu uuuu tmr3 010a timer3 register uuuu uuuu uuuu uuuu pr2 010c period register 2 1111 1111 1111 1111 pr3 010e period register 3 1111 1111 1111 1111 t2con 0110 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? 0000 0000 0000 0000 t3con 0112 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 0000 0000 0000 legend: u = uninitialized bit
dspic30f ds70083g-page 90 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 91 dspic30f 11.0 timer4/5 module this section describes the second 32-bit general pur- pose (gp) timer module (timer4/5) and associated operational modes. figure 11 -1 depicts the simplified block diagram of the 32-bit timer4/5 module. figure 11-2 and figure 11-3 sh ow timer4/5 configured as two independent 16-bit timers, timer4 and timer5, respectively. the timer4/5 module is similar in operation to the timer2/3 module. however, there are some differences which are listed below: the timer4/5 module doe s not support the adc event trigger feature timer4/5 can not be utili zed by other peripheral modules, such as input capture and output compare the operating modes of the timer4/5 module are determined by setting the appropriate bit(s) in the 16-bit t4con and t5con sfrs. for 32-bit timer/counter operation, timer4 is the ls word and timer5 is the ms word of the 32-bit timer. figure 11-1: 32-bit timer4/5 block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: for 32-bit timer operation, t5con control bits are ignored. only t4con control bits are used for setup and control. timer4 clock and gate inputs are utilized for the 32-bit timer module but an interrupt is gen- erated with the timer5 interrupt flag (t5if) and the interrupt is enabled with the timer5 interrupt enable bit (t5ie). note: in some devices, one or more of the t x ck pins may be absent. therefore, for such timers, the following modes should not be used: 1. tcs = 1 (16-bit counter) 2. tcs = 0, tgate = 1 (gated time accumulation) tmr5 tmr4 t5if equal comparator x 32 pr5 pr4 reset lsb msb event flag note: timer configuration bit t32 (t4con<3>) must be set to ? 1 ? for a 32-bit timer/counter operation. all control bits are respective to the t4con register. data bus<15:0> tmr5hld read tmr4 write tmr4 16 16 16 q q d ck tgate (t4con<6>) (t4con<6>) tgate 0 1 ton tckps<1:0> prescaler 1, 8, 64, 256 2 t cy tcs 1 x 0 1 tgate 0 0 gate t4ck sync sync
dspic30f ds70083g-page 92 preliminary ? 2004 microchip technology inc. figure 11-2: 16-bit timer4 block diagram figure 11-3: 16-bit timer5 block diagram ton sync pr4 t4if equal comparator x 16 tmr4 reset event flag tgate tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 tcs 1 x 0 1 tgate 0 0 gate t4ck sync q q d ck ton pr5 t5if equal comparator x 16 tmr5 reset event flag tgate tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 tcs 1 x 0 1 tgate 0 0 t5ck adc event trigger sync q q d ck
? 2004 microchip technology inc. preliminary ds70083g-page 93 dspic30f table 11-1: timer4/5 register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state tmr4 0114 timer 4 register uuuu uuuu uuuu uuuu tmr5hld 0116 timer 5 holding register (for 32-bit operations only) uuuu uuuu uuuu uuuu tmr5 0118 timer 5 register uuuu uuuu uuuu uuuu pr4 011a period register 4 1111 1111 1111 1111 pr5 011c period register 5 1111 1111 1111 1111 t4con 011e ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t45 ?tcs ? 0000 0000 0000 0000 t5con 0120 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 0000 0000 0000 legend: u = uninitialized
dspic30f ds70083g-page 94 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 95 dspic30f 12.0 input capture module this section describes the input capture module and associated operational mode s. the features provided by this module are useful in applications requiring fre- quency (period) and pulse measurement. figure 12-1 depicts a block diagram of the input capture module. input capture is useful for such modes as: frequency/period/pulse measurements additional sources of external interrupts the key operational featur es of the input capture module are: simple capture event mode timer2 and timer3 mode selection interrupt on input capture event these operating modes are determined by setting the appropriate bits in the icxcon register (where x = 1,2,...,n). the dspic de vices contain up to 8 capture channels (i.e., the maximum value of n is 8). figure 12-1: input capture mode block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). icxbuf prescaler icx pin icm<2:0> mode select 3 note: where ?x? is shown, reference is made to the register s or bits associated to the respective input capture channels 1 through n. 10 set flag icxif ictmr t2_cnt t3_cnt edge detection logic clock synchronizer 1, 4, 16 from gp timer module 16 16 fifo r/w logic ici<1:0> icbne, icov icxcon interrupt logic set flag icxif data bus
dspic30f ds70083g-page 96 preliminary ? 2004 microchip technology inc. 12.1 simple capture event mode the simple capture events in the dspic30f product family are: capture every falling edge capture every rising edge capture every 4th rising edge capture every 16th rising edge capture every rising and falling edge these simple input capture modes are configured by setting the appropriate bits icm<2:0> (icxcon<2:0>). 12.1.1 capture prescaler there are four input capture prescaler settings speci- fied by bits icm<2:0> (icxcon<2:0>). whenever the capture channel is turned off, the prescaler counter will be cleared. in addition, any reset will clear the prescaler counter. 12.1.2 capture buffer operation each capture channel has an associated fifo buffer which is four 16-bit words deep. there are two status flags which provide status on the fifo buffer: icbfne - input capture buffer not empty icov - input capture overflow the icbfne will be set on the first input capture event and remain set until all capt ure events have been read from the fifo. as each word is read from the fifo, the remaining words are advanced by one position within the buffer. in the event that the fifo is full with four capture events and a fifth capture event occurs prior to a read of the fifo, an overflow c ondition will occur and the icov bit will be set to a logic ? 1 ?. the fifth capture event is lost and is not stored in the fifo. no additional events will be captured until all four events have been read from the buffer. if a fifo read is performed after the last read and no new capture event has be en received, the read will yield indeterminate results. 12.1.3 timer2 and timer3 selection mode the input capture module cons ists of up to 8 input cap- ture channels. each channel can select between one of two timers for the time base, timer2 or timer3. selection of the timer resource is accomplished through sfr bit, ictmr (icxcon<7>). timer3 is the default timer resource available for the input capture module. 12.1.4 hall sensor mode when the input capture module is set for capture on every edge, rising and falling, icm<2:0> = 001 , the fol- lowing operations are performed by the input capture logic: the input capture interr upt flag is set on every edge, rising and falling. the interrupt on capture mode setting bits, ici<1:0>, is ignored since every capture generates an interrupt. a capture overflow condit ion is not generated in this mode.
? 2004 microchip technology inc. preliminary ds70083g-page 97 dspic30f 12.2 input capture operation during sleep and idle modes an input capture event will generate a device wake-up or interrupt, if enabled, if the device is in cpu idle or sleep mode. independent of the timer bei ng enabled, the input cap- ture module will wake-up from the cpu sleep or idle mode when a capture event occurs if icm<2:0> = 111 and the interrupt enable bit is asserted. the same wake- up can generate an interrupt if the conditions for pro- cessing the interrupt have been satisfied. the wake-up feature is useful as a method of adding extra external pin interrupts. 12.2.1 input capture in cpu sleep mode cpu sleep mode allows in put capture module opera- tion with reduced functionali ty. in the cpu sleep mode, the ici<1:0> bits are not applicable and the input cap- ture module can only function as an external interrupt source. the capture module must be configured for interrupt only on rising edge (icm<2:0> = 111 ) in order for the input capture module to be used while the device is in sleep mode. the prescale sett ings of 4:1 or 16:1 are not applicable in this mode. 12.2.2 input capture in cpu idle mode cpu idle mode allows inpu t capture module operation with full functionality. in the cpu idle mode, the inter- rupt mode selected by the ici<1:0> bits is applicable, as well as the 4:1 and 16:1 capture prescale settings which are defined by contro l bits icm<2:0>. this mode requires the selected timer to be enabled. moreover, the icsidl bit must be asserted to a logic ? 0 ?. if the input capture module is defined as icm<2:0> = 111 in cpu idle mode, the input capture pin will serve only as an external interrupt pin. 12.3 input capture interrupts the input capture channels ha ve the ability to generate an interrupt based upon the selected number of cap- ture events. the selection nu mber is set by control bits ici<1:0> (icxcon<6:5>). each channel provides an in terrupt flag (icxif) bit. the respective capture channel in terrupt flag is located in the corresponding ifsx status register. enabling an interrupt is ac complished via the respec- tive capture channel interrupt enable (icxie) bit. the capture interrupt enable bit is located in the corresponding iec control register.
dspic30f ds70083g-page 98 preliminary ? 2004 microchip technology inc. table 12-1: input capture register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state ic1buf 0140 input 1 capture register uuuu uuuu uuuu uuuu ic1con 0142 ? ?icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic2buf 0144 input 2 capture register uuuu uuuu uuuu uuuu ic2con 0146 ? ?icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic3buf 0148 input 3 capture register uuuu uuuu uuuu uuuu ic3con 014a ? ?icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic4buf 014c input 4 capture register uuuu uuuu uuuu uuuu ic4con 014e ? ?icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic5buf 0150 input 5 capture register uuuu uuuu uuuu uuuu ic5con 0152 ? ?icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic6buf 0154 input 6 capture register uuuu uuuu uuuu uuuu ic6con 0156 ? ?icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic7buf 0158 input 7 capture register uuuu uuuu uuuu uuuu ic7con 015a ? ?icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 ic8buf 015c input 8 capture register uuuu uuuu uuuu uuuu ic8con 015e ? ?icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 0000 0000 0000 legend: u = uninitialized bit
? 2004 microchip technology inc. preliminary ds70083g-page 99 dspic30f 13.0 output compare module this section describes the output compare module and associated operational mode s. the features provided by this module are useful in applications requiring operational modes, such as: generation of variable width output pulses power factor correction figure 13-1 depicts a bloc k diagram of the output compare module. the key operational features of the output compare module include: timer2 and timer3 selection mode simple output compare match mode dual output compare match mode simple pwm mode output compare during sleep and idle modes interrupt on output compare/pwm event these operating modes are determined by setting the appropriate bits in the 16-bit ocxcon sfr (where x = 1,2,3,...,n). the dspic de vices contain up to 8 compare channels (i.e., the maximum value of n is 8). ocxrs and ocxr in figure 13-1 represent the dual compare registers. in the dual compare mode, the ocxr register is used for the first compare and ocxrs is used for the second compare. figure 13-1: output compare mode block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). ocxr comparator output logic q s r ocm<2:0> output ocx set flag bit ocxif ocxrs mode select 3 note: where ?x? is shown, reference is made to the regist ers associated with the respective output compare channels 1 through n. ocfa octsel 01 t2p2_match tmr2<15:0 tmr3<15:0> t3p3_match from gp (for x = 1, 2, 3 or 4) or ocfb (for x = 5, 6, 7 or 8) 01 timer module enable
dspic30f ds70083g-page 100 preliminary ? 2004 microchip technology inc. 13.1 timer2 and timer3 selection mode each output compare channel can select between one of two 16-bit timers, timer2 or timer3. the selection of the timers is controlled by the octsel bit (ocxcon<3>). timer2 is the default timer resource for the output compare module. 13.2 simple output compare match mode when control bits ocm<2:0> (ocxcon<2:0>) = 001 , 010 or 011 , the selected output compare channel is configured for one of three simple output compare match modes: compare forces i/o pin low compare forces i/o pin high compare toggles i/o pin the ocxr register is used in these modes. the ocxr register is loaded with a value and is compared to the selected incrementing timer count. when a compare occurs, one of these compare match modes occurs. if the counter resets to zero before reaching the value in ocxr, the state of the ocx pin remains unchanged. 13.3 dual output compare match mode when control bits ocm<2:0> (ocxcon<2:0>) = 100 or 101 , the selected output compare channel is config- ured for one of two dual output compare modes, which are: single output pulse mode continuous output pulse mode 13.3.1 single pulse mode for the user to configure the module for the generation of a single output pulse, the following steps are required (assuming timer is off): determine instruction cycle time t cy . calculate desired pulse width value based on t cy . calculate time to start pul se from timer start value of 0x0000 . write pulse width start and stop times into ocxr and ocxrs compare r egisters (x denotes channel 1, 2, ...,n). set timer period register to value equal to, or greater than value in ocxrs compare register. set ocm<2:0> = 100 . enable timer, ton (txcon<15>) = 1 . to initiate another single pulse, issue another write to set ocm<2:0> = 100 . 13.3.2 continuous pulse mode for the user to configure t he module for the generation of a continuous stream of output pulses, the following steps are required: determine instruction cycle time t cy . calculate desired pulse value based on t cy . calculate timer to start pulse width from timer start value of 0x0000 . write pulse width start and stop times into ocxr and ocxrs (x denotes channel 1, 2, ...,n) compare registers, respectively. set timer period register to value equal to, or greater than value in ocxrs compare register. set ocm<2:0> = 101 . enable timer, ton (txcon<15>) = 1 . 13.4 simple pwm mode when control bits ocm<2:0> (ocxcon<2:0>) = 110 or 111 , the selected output co mpare channel is config- ured for the pwm mode of operation. when configured for the pwm mode of operation , ocxr is the main latch (read only) and ocxrs is th e secondary latch. this enables glitchless pwm transitions. the user must perform the following steps in order to configure the output compare module for pwm operation: 1. set the pwm period by writing to the appropriate period register. 2. set the pwm duty cycle by writing to the ocxrs register. 3. configure the output compare module for pwm operation. 4. set the tmrx prescale value and enable the timer, ton (txcon<15>) = 1 . 13.4.1 input pin fault protection for pwm when control bits ocm<2:0> (ocxcon<2:0>) = 111 , the selected output compar e channel is again config- ured for the pwm mode of op eration with the additional feature of input fault protection. while in this mode, if a logic ? 0 ? is detected on the ocfa/b pin, the respec- tive pwm output pin is placed in the high impedance input state. the ocflt bit (ocxcon<4>) indicates whether a fault condition has occurred. this state will be maintained until both of the following events have occurred: the external fault condition has been removed. the pwm mode has been re-enabled by writing to the appropriate control bits.
? 2004 microchip technology inc. preliminary ds70083g-page 101 dspic30f 13.4.2 pwm period the pwm period is specified by writing to the prx register. the pwm period can be calculated using equation 13-1. equation 13-1: pwm frequency is defined as 1 / [pwm period]. when the selected tmrx is equal to its respective period register, prx, the following four events occur on the next increment cycle: tmrx is cleared. the ocx pin is set. - exception 1: if pwm duty cycle is 0x0000 , the ocx pin will remain low. - exception 2: if duty cycle is greater than prx, the pin will remain high. the pwm duty cycle is latched from ocxrs into ocxr. the corresponding timer interrupt flag is set. see figure 13-2 for key pwm period comparisons. timer3 is referred to in figure 13-2 for clarity. figure 13-2: pwm output timing 13.5 output compare operation during cpu sleep mode when the cpu enters sleep mode, all internal clocks are stopped. therefore, when the cpu enters the sleep state, the output comp are channel will drive the pin to the active state t hat was observed prior to entering the cpu sleep state. for example, if the pin was high when the cpu entered the sleep state, the pin will remain high. likewise, if the pin was low when the cpu en tered the sleep state, the pin will remain low. in eit her case, the output compare module will resume operat ion when the device wakes up. 13.6 output compare operation during cpu idle mode when the cpu enters the idle mode, the output compare module can operate with full functionality. the output compare channel will operate during the cpu idle mode if the ocsi dl bit (ocxcon<13>) is at logic ? 0 ? and the selected time base (timer2 or timer3) is enabled and the tsidl bit of the selected timer is set to logic ? 0 ?. 13.7 output compare interrupts the output compare channels have the ability to gener- ate an interrupt on a comp are match, for whichever match mode has been selected. for all modes except the pwm mode, when a compare event occurs, the respective interrupt flag (ocxif) is asserted and an interrupt will be generated if enabled. the ocxif bit is located in the corresponding ifs status register and must be cleared in software. the interrupt is enabled via the respective compare inter- rupt enable (ocxie) bit lo cated in the corresponding iec control register. for the pwm mode, when an event occurs, the respec- tive timer interrupt flag (t 2if or t3if) is asserted and an interrupt will be generated if enabled. the if bit is located in the ifs0 status register and must be cleared in software. the interrupt is enabled via the respective timer interrupt enable bit (t 2ie or t3ie) located in the iec0 control register. the output compare interrupt flag is never set during the pwm mode of operation. pwm period = [(prx) + 1] 4 t osc (tmrx prescale value) period duty cycle tmr3 = duty cycle tmr3 = duty cycle tmr3 = pr3 t3if = 1 (interrupt flag) ocxr = ocxrs tmr3 = pr3 (interrupt flag) ocxr = ocxrs t3if = 1 (ocxr) (ocxr)
dspic30f ds70083g-page 102 preliminary ? 2004 microchip technology inc. table 13-1: output compare register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state oc1rs 0180 output compare 1 secondary register 0000 0000 0000 0000 oc1r 0182 output compare 1 main register 0000 0000 0000 0000 oc1con 0184 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 oc2rs 0186 output compare 2 secondary register 0000 0000 0000 0000 oc2r 0188 output compare 2 main register 0000 0000 0000 0000 oc2con 018a ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octse ocm<2:0> 0000 0000 0000 0000 oc3rs 018c output compare 3 secondary register 0000 0000 0000 0000 oc3r 018e output compare 3 main register 0000 0000 0000 0000 oc3con 0190 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 oc4rs 0192 output compare 4 secondary register 0000 0000 0000 0000 oc4r 0194 output compare 4 main register 0000 0000 0000 0000 oc4con 0196 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 oc5rs 0198 output compare 5 secondary register 0000 0000 0000 0000 oc5r 019a output compare 5 main register 0000 0000 0000 0000 oc5con 019c ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 oc6rs 019e output compare 6 secondary register 0000 0000 0000 0000 oc6r 01a0 output compare 6 main register 0000 0000 0000 0000 oc6con 01a2 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 oc7rs 01a4 output compare 7 secondary register 0000 0000 0000 0000 oc7r 01a6 output compare 7 main register 0000 0000 0000 0000 oc7con 01a8 ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 oc8rs 01aa output compare 8 secondary register 0000 0000 0000 0000 oc8r 01ac output compare 8 main register 0000 0000 0000 0000 oc8con 01ae ? ?ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 0000 0000 0000 legend: u = uninitialized bit
? 2004 microchip technology inc. preliminary ds70083g-page 103 dspic30f 14.0 spi module the serial peripheral interface (spi) module is a syn- chronous serial interface. it is useful for communicating with other periphera l devices, such as eeproms, shift registers, display drivers and a/d converters, or other microcontrollers. it is compat ible with motorola's spi? and siop interfaces. 14.1 operating function description each spi module consists of a 16-bit shift register, spixsr (where x = 1 or 2), used for shifting data in and out, and a buffer register, spixbuf. a control register, spixcon, configures the module. additionally, a status register, spixstat, indicates various status conditions. the serial interface consists of 4 pins: sdix (serial data input), sdox (serial data output), sckx (shift clock input or output), and ssx (active low slave select). in master mode operation, sck is a clock output but in slave mode, it is a clock input. a series of eight (8) or si xteen (16) clock pulses shift out bits from the spixsr to sdox pin and simulta- neously shift in data from sd ix pin. an interrupt is gen- erated when the transfer is complete and the corresponding interrupt flag bit (spi1if or spi2if) is set. this interrupt can be dis abled through an interrupt enable bit (spi1ie or spi2ie). the receive operation is double-buffered. when a com- plete byte is received, it is transferred from spixsr to spixbuf. if the receive buffer is full when new data is being trans- ferred from spixsr to spi xbuf, the module will set the spirov bit indicating an over flow condition. the trans- fer of the data from spixsr to spixbuf will not be completed and the new data will be lost. the module will not respond to scl tran sitions while spirov is ? 1 ?, effectively disabling the module until spixbuf is read by user software. transmit writes are also double-buffered. the user writes to spixbuf. when th e master or slave transfer is completed, the contents of the shift register (spixsr) are moved to the receive buffer. if any transmit data has been written to the buffer register, the contents of the transmit buffer are moved to spixsr. the received data is thus placed in spixbuf and the transmit data in spixsr is ready for the next transfer. in master mode, the clock is generated by prescaling the system clock. data is transmitted as soon as a value is written to spixbuf. the interrupt is generated at the middle of the transfer of the last bit. in slave mode, data is tr ansmitted and received as external clock pulses appear on sck. again, the inter- rupt is generated when the la st bit is latched. if ssx control is enabled, then trans mission and reception are enabled only when ssx = low. the sdox output will be disabled in ssx mode with ssx high. the clock provided to the module is (f osc /4). this clock is then prescaled by the primary (ppre<1:0>) and the secondary (spre<2:0> ) prescale factors. the cke bit determines whether tr ansmit occurs on transi- tion from active clock state to idle clock state, or vice versa. the ckp bit selects th e idle state (high or low) for the clock. 14.1.1 word and byte communication a control bit, mode16 (spixcon<10>), allows the module to communicate in ei ther 16-bit or 8-bit mode. 16-bit operation is identical to 8-bit operation except that the number of bits tran smitted is 16 instead of 8. the user software must d isable the module prior to changing the mode16 bit. the spi module is reset when the mode16 bit is changed by the user. a basic difference between 8-bi t and 16-bit operation is that the data is transmitted out of bit 7 of the spixsr for 8-bit operation, and data is transmitted out of bit15 of the spixsr for 16-bit operati on. in both modes, data is shifted into bit 0 of the spixsr. 14.1.2 sdox disable a control bit, dissdo, is pr ovided to the spixcon reg- ister to allow the sdox out put to be disabled. this will allow the spi module to be connected in an input only configuration. sdo can also be used for general purpose i/o. 14.2 framed spi support the module supports a ba sic framed spi protocol in master or slave mode. the control bit frmen enables framed spi support and causes the ssx pin to perform the frame synchronization pulse (fsync) function. the control bit spifsd determines whether the ssx pin is an input or an output (i.e., whether the module receives or generates the frame synchronization pulse). the frame pulse is an active high pulse for a single spi clock cycle. when frame synchronization is enabled, the data transm ission starts only on the subsequent transmit edge of the spi clock. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: both the transmit buffer (spixtxb) and the receive buffer (spixrxb) are mapped to the same register address, spixbuf.
dspic30f ds70083g-page 104 preliminary ? 2004 microchip technology inc. figure 14-1: spi block diagram figure 14-2: spi master/slave connection note: x = 1 or 2. read write internal data bus sdix sdox ssx sckx spixsr spixbuf bit 0 shift clock edge select f cy primary 1, 4, 16, 64 enable master clock prescaler secondary prescaler 1,2,4,6,8 ss and fsync control clock control transmit spixbuf receive serial input buffer (spixbuf) shift register (spixsr) msb lsb sdox sdix processor 1 sckx spi master serial input buffer (spiybuf) shift register (spiysr) lsb msb sdiy sdoy processor 2 scky spi slave serial clock note: x = 1 or 2, y = 1 or 2.
? 2004 microchip technology inc. preliminary ds70083g-page 105 dspic30f 14.3 slave select synchronization the ssx pin allows a synchronous slave mode. the spi must be configured in spi slave mode with ssx pin control enabled (ssen = 1 ). when the ssx pin is low, transmission and recepti on are enabled and the sdox pin is driven. when ssx pin goes high, the sdox pin is no longer driven. also, the spi module is re- synchronized, and all counte rs/control circuitry are reset. therefore, when the ssx pin is asserted low again, transmission/reception will begin at the ms bit even if ssx had been de-asserted in the middle of a transmit/receive. 14.4 spi operation during cpu sleep mode during sleep mode, the spi module is shutdown. if the cpu enters sleep mode while an spi transaction is in progress, then the transmission and reception is aborted. the transmitter and receiver will stop in sleep mode. however, register contents are not affected by entering or exiting sleep mode. 14.5 spi operation during cpu idle mode when the device enters idle mode, all clock sources remain functional. the spi sidl bit (spixstat<13>) selects if the spi module will stop or continue on idle. if spisidl = 0 , the module will cont inue to operate when the cpu enters idle mode. if spisidl = 1 , the module will stop when the cpu enters idle mode.
dspic30f ds70083g-page 106 preliminary ? 2004 microchip technology inc. table 14-1: spi1 register map table 14-2: spi2 register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state spi1stat 0220 spien ? spisidl ? ? ? ? ? ?spirov ? ? ? ? spitbf spirbf 0000 0000 0000 0000 spi1con 0222 ? frmen spifsd ? dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 0000 0000 0000 spi1buf 0224 transmit and receive buffer 0000 0000 0000 0000 legend: u = uninitialized bit sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state spi2stat 0226 spien ?spisidl ? ? ? ? ? ?spirov ? ? ? ? spitbf spirbf 0000 0000 0000 0000 spi2con 0228 ? frmen spifsd ? dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 0000 0000 0000 spi2buf 022a transmit and receive buffer 0000 0000 0000 0000 legend: u = uninitialized bit
? 2004 microchip technology inc. preliminary ds70083g-page 107 dspic30f 15.0 i 2 c module the inter-integrated circuit (i 2 c tm ) module provides complete hardware support for both slave and multi- master modes of the i 2 c serial communication standard, with a 16-bit interface. this module offers the following key features: i 2 c interface supporting both master and slave operation. i 2 c slave mode supports 7 and 10-bit address. i 2 c master mode supports 7 and 10-bit address. i 2 c port allows bidirect ional transfers between master and slaves. serial clock synchronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control). i 2 c supports multi-master operation; detects bus collision and will arbitrate accordingly. 15.1 operating function description the hardware fully implements all the master and slave functions of the i 2 c standard and fast mode specifications, as well as 7 and 10-bit addressing. thus, the i 2 c module can operate either as a slave or a master on an i 2 c bus. 15.1.1 various i 2 c modes the following types of i 2 c operation are supported: i 2 c slave operation with 7-bit address i 2 c slave operation with 10-bit address i 2 c master operation with 7 or 10-bit address see the i 2 c programmer?s model in figure 15-1. figure 15-1: programmer?s model 15.1.2 pin configuration in i 2 c mode i 2 c has a 2-pin interface: th e scl pin is clock and the sda pin is data. 15.1.3 i 2 c registers i2ccon and i2cstat are control and status registers, respectively. the i2ccon reg ister is readable and writ- able. the lower 6 bits of i2cstat are read only. the remaining bits of the i2cstat are read/write. i2crsr is the shift register used for shifting data, whereas i2crcv is the buffer register to which data bytes are written, or from which data bytes are read. i2crcv is the receive buffer as shown in figure 15-1. i2ctrn is the transmit register to which bytes are written during a transmit operation, as shown in figure 15-2. the i2cadd register holds t he slave address. a status bit, add10, indicates 10 -bit address mode. the i2cbrg acts as the baud ra te generator reload value. in receive operations, i2crsr and i2crcv together form a double-buffered receiver. when i2crsr receives a complete byte, it is transferred to i2crcv and an interrupt pulse is generated. during transmission, the i2ctrn is not double-buffered. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). bit 7 bit 0 i2crcv (8 bits) bit 7 bit 0 i2ctrn (8 bits) bit 8 bit 0 i2cbrg (9 bits) bit 15 bit 0 i2ccon (16 bits) bit 15 bit 0 i2cstat (16 bits) bit 9 bit 0 i2cadd (10 bits) note: following a restart condition in 10-bit mode, the user only needs to match the first 7-bit address.
dspic30f ds70083g-page 108 preliminary ? 2004 microchip technology inc. figure 15-2: i 2 c block diagram i2crsr i2crcv internal data bus scl sda shift match detect i2cadd start and stop bit detect clock addr_match clock stretching i2ctrn lsb shift clock write read brg down i2cbrg reload control f osc start, restart, stop bit generate write read acknowledge generation collision detect write read write read i2ccon write read i2cstat control logic read lsb counter
? 2004 microchip technology inc. preliminary ds70083g-page 109 dspic30f 15.2 i 2 c module addresses the i2cadd register contains the slave mode addresses. the register is a 10-bit register. if the a10m bit (i2ccon<10>) is ? 0 ?, the address is interpreted by the module as a 7-bit address. when an address is received, it is compared to the 7 ls bits of the i2cadd register. if the a10m bit is ? 1 ?, the address is assumed to be a 10-bit address. when an address is received, it will be compared with the binary value ? 11110 a9 a8 ? (where a9 and a8 are two most signific ant bits of i2cadd). if that value matches, the ne xt address will be compared with the least significant 8 bi ts of i2cadd, as specified in the 10-bit addressing protocol. 7-bit i 2 c slave addresses supported by dspic30f: 15.3 i 2 c 7-bit slave mode operation once enabled (i2cen = 1 ), the slave module will wait for a start bit to occur (i.e., the i 2 c module is ?idle?). fol- lowing the detection of a start bit, 8 bits are shifted into i2crsr and the address is compared against i2cadd. in 7-bit mode (a10m = 0 ), bits i2cadd<6:0> are compared against i2crsr<7:1> and i2crsr<0> is the r_w bit. all incoming bits are sampled on the ris- ing edge of scl. if an address match occurs , an acknowledgement will be sent, and the slave event interrupt flag (si2cif) is set on the falling ed ge of the ninth (ack ) bit. the address match does not affect the contents of the i2crcv buffer or the rbf bit. 15.3.1 slave transmission if the r_w bit received is a ? 1 ?, then the serial port will go into transmit mode. it will send ack on the ninth bit and then hold scl to ? 0 ? until the cpu responds by writ- ing to i2ctrn. scl is released by setting the sclrel bit, and 8 bits of data are shifted out. data bits are shifted out on the falling edge of scl, such that sda is valid during scl high. the inte rrupt pulse is sent on the falling edge of the ninth clo ck pulse, regardless of the status of the ack received from the master. 15.3.2 slave reception if the r_w bit received is a ? 0 ? during an address match, then receive mode is initiated. incoming bits are sampled on the rising edge of scl. after 8 bits are received, if i2crcv is not full or i2cov is not set, i2crsr is transferred to i2crcv. ack is sent on the ninth clock. if the rbf flag is set, indicating that i2crcv is still holding data from a previous operation (rbf = 1 ), then ack is not sent; however, the interrupt pulse is gener- ated. in the case of an overflow, the contents of the i2crsr are not loaded into the i2crcv. 15.4 i 2 c 10-bit slave mode operation in 10-bit mode, the basic receive and transmit opera- tions are the same as in the 7-bit mode. however, the criteria for address match is more complex. the i 2 c specification dictates that a slave must be addressed for a writ e operation with two address bytes following a start bit. the a10m bit is a control bi t that signifies that the address in i2cadd is a 10-bit address rather than a 7-bit address. the address detectio n protocol for the first byte of a message address is identical for 7-bit and 10-bit messages, but the bits bein g compared are different. i2cadd holds the entire 10-bit address. upon receiv- ing an address following a start bit, i2crsr <7:3> is compared against a literal ? 11110 ? (the default 10-bit address) and i2crsr<2:1> are compared against i2cadd<9:8>. if a match occurs and if r_w = 0 , the interrupt pulse is sent. the add10 bit will be cleared to indicate a partial address match. if a match fails or r_w = 1 , the add10 bit is cle ared and the module returns to the idle state. the low byte of the address is then received and com- pared with i2cadd<7:0>. if an address match occurs, the interrupt pulse is gener ated and the add10 bit is set, indicating a complete 10 -bit address match. if an address match did not occur, the add10 bit is cleared and the module returns to the idle state. 15.4.1 10-bit mode slave transmission once a slave is addressed in this fashion with the full 10-bit address (we will refer to this state as ?prior_addr_match?), the master can begin sending data bytes for a sl ave reception operation. 0x00 general call address or start byte 0x01-0x03 reserved 0x04-0x77 valid 7-bit addresses 0x78-0x7b valid 10-bit addresses (lower 7 bits) 0x7c-0x7f reserved note: the i2crcv will be lo aded if the i2cov bit = 1 and the rbf flag = 0 . in this case, a read of the i2crcv was performed but the user did not clear the state of the i2cov bit before the next receive occurred. the acknowledgement is not sent (ack = 1 ) and the i2crcv is updated.
dspic30f ds70083g-page 110 preliminary ? 2004 microchip technology inc. 15.4.2 10-bit mode slave reception once addressed, the master can generate a repeated start, reset the high byte of the address and set the r_w bit without generating a st op bit, thus initiating a slave transmit operation. 15.5 automatic clock stretch in the slave modes, the module can synchronize buffer reads and write to the master device by clock stretching. 15.5.1 transmit clock stretching both 10-bit and 7-bit transmit modes implement clock stretching by asserting the sclrel bit after the falling edge of the ninth clock, if the tbf bit is cleared, indicat- ing the buffer is empty. in slave transmit modes, clock stretching is always performed irrespective of the stren bit. clock synchronization takes place following the ninth clock of the transmit sequence. if the device samples an ack on the falling edge of t he ninth clock and if the tbf bit is still clear, then th e sclrel bit is automati- cally cleared. the sclrel being cleared to ? 0 ? will assert the scl line low. the user?s isr must set the sclrel bit before transmission is allowed to continue. by holding the scl line low, the user has time to ser- vice the isr and load the contents of the i2ctrn before the master device can initiate another transmit sequence. 15.5.2 receive clock stretching the stren bit in the i2ccon register can be used to enable clock stretching in slave receive mode. when the stren bit is set, the scl pi n will be held low at the end of each data receive sequence. 15.5.3 clock stretching during 7-bit addressing (stren = 1 ) when the stren bit is set in slave receive mode, the scl line is held low when the buffer register is full. the method for stretching the scl output is the same for both 7 and 10-bit addressing modes. clock stretching takes place following the ninth clock of the receive sequence. on th e falling edge of the ninth clock at the end of the ack sequence, if the rbf bit is set, the sclrel bit is auto matically cleared, forcing the scl output to be held lo w. the user?s isr must set the sclrel bit before recept ion is allowed to continue. by holding the scl line low, the user has time to ser- vice the isr and read the contents of the i 2 crcv before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring. 15.5.4 clock stretching during 10-bit addressing (stren = 1 ) clock stretching takes pl ace automatically during the addressing sequence. beca use this module has a register for the entire addre ss, it is not necessary for the protocol to wait for the address to be updated. after the address phase is complete, clock stretching will occur on each data rece ive or transmit sequence as was described earlier. 15.6 software controlled clock stretching (stren = 1 ) when the stren bit is ? 1 ?, the sclrel bit may be cleared by software to allow software to control the clock stretching. the logic wi ll synchronize writes to the sclrel bit with the scl clock. clearing the sclrel bit will not assert the scl output until the module detects a falling edge on the scl output and scl is sampled low. if the sclrel bit is cleared by the user while the scl line has been sampled low, the scl out- put will be asserted (held low). the scl output will remain low until the sclrel bit is set, and all other devices on the i 2 c bus have de-asserted scl. this ensures that a write to the sclrel bit will not violate the minimum high time requirement for scl. if the stren bit is ? 0 ?, a software write to the sclrel bit will be disregarded and have no effect on the sclrel bit. 15.7 interrupts the i 2 c module generates two interrupt flags, mi2cif (i 2 c master interrupt flag) and si2cif (i 2 c slave inter- rupt flag). the mi2cif interrupt flag is activated on completion of a master message event. the si2cif interrupt flag is activated on detection of a message directed to the slave. note 1: if the user loads the contents of i2ctrn, setting the tbf bit be fore the falling edge of the ninth clock, the sclrel bit will not be cleared and clock stretching will not occur. 2: the sclrel bit can be set in software, regardless of the state of the tbf bit. note 1: if the user reads the contents of the i2crcv, clearing the rbf bit before the falling edge of the ninth clock, the sclrel bit will not be cleared and clock stretching will not occur. 2: the sclrel bit can be set in software regardless of the state of the rbf bit. the user should be careful to clear the rbf bit in the isr before the next receive sequence in order to prevent an overflow condition.
? 2004 microchip technology inc. preliminary ds70083g-page 111 dspic30f 15.8 slope control the i 2 c standard requires slope control on the sda and scl signals for fast mode (400 khz). the control bit, disslw, enables the user to disable slew rate con- trol if desired. it is necessary to disable the slew rate control for 1 mhz mode. 15.9 ipmi support the control bit, ipmien, enabl es the module to support intelligent peripheral mana gement interface (ipmi). when this bit is set, the mo dule accepts and acts upon all addresses. 15.10 general call address support the general call address can address all devices. when this address is used, all devices should, in theory, respond with an acknowledgement. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r_w = 0 . the general call address is recognized when the gen- eral call enable (gcen) bit is set (i2ccon<15> = 1 ). following a start bit detection, 8 bits are shifted into i2crsr and the address is compared with i2cadd, and is also compared with the general call address which is fixed in hardware. if a general call address match occurs, the i2crsr is transferred to the i2crcv af ter the eighth clock, the rbf flag is set and on the fall ing edge of the ninth bit (ack bit), the master event interrupt flag (mi2cif) is set. when the interrupt is servic ed, the source for the inter- rupt can be checked by reading the contents of the i2crcv to determine if the address was device specific or a general call address. 15.11 i 2 c master support as a master device, six o perations are supported: assert a start condition on sda and scl. assert a restart condition on sda and scl. write to the i2ctrn register initiating transmission of data/address. generate a stop condition on sda and scl. configure the i 2 c port to receive data. generate an ack condition at the end of a received byte of data. 15.12 i 2 c master operation the master device generate s all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeat ed start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mo de, serial data is output through sda, while scl outp uts the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) a nd the data direction bit. in this case, the data direct ion bit (r_w) is logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmitted, an ack bit is received. start and stop con- ditions are output to indica te the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the data directi on bit. in this case, the data direction bit (r_w) is logic ? 1 ?. thus, the first byte trans- mitted is a 7-bit slave address, followed by a ? 1 ? to indi- cate receive bit. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an ack bit is transmitted. start and stop conditions indicate the beginning and end of transmission. 15.12.1 i 2 c master transmission transmission of a data byte, a 7-bit address, or the sec- ond half of a 10-bit addres s is accomplished by simply writing a value to i2ctrn register. the user should only write to i2ctrn when the module is in a wait state. this action will set the buffer full flag (tbf) and allow the baud rate generat or to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted. the transmit status flag, trstat (i2cstat<14>), indicates that a master transmit is in progress. 15.12.2 i 2 c master reception master mode reception is enabled by programming the receive enable bit, rcen (i2ccon<11>). the i 2 c module must be idle before the rcen bit is set, other- wise the rcen bit wi ll be disregarded. the baud rate generator begins counting and on each rollover, the state of the scl pin ack and data are shifted into the i2crsr on the rising edge of each clock.
dspic30f ds70083g-page 112 preliminary ? 2004 microchip technology inc. 15.12.3 baud rate generator in i 2 c master mode, the rel oad value for the brg is located in the i2cbrg register. when the brg is loaded with this value, t he brg counts down to ? 0 ? and stops until another reload has taken place. if clock arbi- tration is taking place, for in stance, the br g is reloaded when the scl pin is sampled high. as per the i 2 c standard, f scl may be 100 khz or 400 khz. however, the user can specify any baud rate up to 1 mhz. i2cbrg values of ? 0 ? or ? 1 ? are illegal. equation 15-1: serial clock rate 15.12.4 clock arbitration clock arbitration occurs wh en the master de-asserts the scl pin (scl allowed to float high) during any receive, transmit, or restart/stop condition. when the scl pin is allowed to fl oat high, the baud rate gen- erator (brg) is suspended from counting until the scl pin is actually sampled high . when the scl pin is sam- pled high, the baud rate gene rator is reloaded with the contents of i2cbrg and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device. 15.12.5 multi-master communication, bus collision, and bus arbitration multi-master operation suppor t is achieved by bus arbi- tration. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda by letting sda float high while another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the mi2cif pulse and reset the master portion of the i 2 c port to its idle state. if a transmit was in progress when the bus collision occurred, the transmission is halted, the tbf flag is cleared, the sda and scl lines are de-asserted and a value can now be written to i2ctrn. when the user services the i 2 c master event interrupt service rou- tine, if the i 2 c bus is free (i.e., the p bit is set), the user can resume communication by asserting a start condition. if a start, restart, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are de- asserted, and the respective control bits in the i2ccon register are cleared to ? 0 ?. when the user services the bus collision interrupt servic e routine, and if the i 2 c bus is free, the user ca n resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins, and if a stop condition occurs, the mi2cif bit will be set. a write to the i2ctrn will st art the transmission of data at the first data bit regardles s of where the transmitter left off when bus collision occurred. in a multi-master environment, the interrupt generation on the detection of start and stop conditions allows the determination of when the bu s is free. control of the i 2 c bus can be taken when the p bit is set in the i2cstat register, or the bus is idle and the s and p bits are cleared. 15.13 i 2 c module operation during cpu sleep and idle modes 15.13.1 i 2 c operation during cpu sleep mode when the device enters sl eep mode, all clock sources to the module are shutdown and stay at logic ? 0 ?. if sleep occurs in the middle of a transmission and the state machine is partially into a transmission as the clocks stop, then the transmission is aborted. similarly, if sleep occurs in the middle of a reception, then the reception is aborted. 15.13.2 i 2 c operation during cpu idle mode for the i 2 c, the i2csidl bit sele cts if the module will stop on idle or continue on idle. if i2csidl = 0 , the module will continue operati on on assertion of the idle mode. if i2csidl = 1 , the module will stop on idle. i2cbrg = f cy f cy f scl 1,111,111 ? 1 ? ()
? 2004 microchip technology inc. preliminary ds70083g-page 113 dspic30f table 15-1: i 2 c register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state i2crcv 0200 ? ? ? ? ? ? ? ? receive register 0000 0000 0000 0000 i2ctrn 0202 ? ? ? ? ? ? ? ? transmit register 0000 0000 1111 1111 i2cbrg 0204 ? ? ? ? ? ? ? baud rate generator 0000 0000 0000 0000 i2ccon 0206 i2cen ? i2csidl sclrel ipmien a10m disslw sm en gcen stren ackdt acken rcen pen rsen sen 0001 0000 0000 0000 i2cstat 0208 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 0000 0000 0000 i2cadd 020a ? ? ? ? ? ? address register 0000 0000 0000 0000 legend: u = uninitialized bit
dspic30f ds70083g-page 114 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 115 dspic30f 16.0 universal asynchronous receiver transmitter (uart) module this section describes th e universal asynchronous receiver/transmitter communications module. 16.1 uart module overview the key features of the uart module are: full-duplex, 8 or 9-bit data communication even, odd or no parity options (for 8-bit data) one or two stop bits fully integrated baud rate generator with 16-bit prescaler baud rates range from 38 bps to 1.875 mbps at a 30 mhz instruction rate 4-word deep transmit data buffer 4-word deep receive data buffer parity, framing and buffer overrun error detection support for interrupt only on address detect (9th bit = 1 ) separate transmit and receive interrupts loopback mode for diagnostic support figure 16-1: uart transmitter block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). write write utx8 uxtxreg low byte load tsr transmit control ? control tsr ? control buffer ? generate flags ? generate interrupt control and status bits uxtxif data ? 0 ? (start) ? 1 ? (stop) parity parity generator transmit shift register (uxtsr) 16 divider control signals 16x baud clock from baud rate generator internal data bus utxbrk uxtx note: x = 1 or 2.
dspic30f ds70083g-page 116 preliminary ? 2004 microchip technology inc. figure 16-2: uart receiver block diagram read urx8 uxrxreg low byte load rsr uxmode receive buffer control ? generate flags ? generate interrupt uxrxif uxrx start bit detect receive shift register 16 divider control signals uxsta ? shift data characters read read write write to buffer 8-9 (uxrsr) perr ferr parity check stop bit detect shift clock generation wake logic 16 internal data bus 1 0 lpback from uxtx 16x baud clock from baud rate generator
? 2004 microchip technology inc. preliminary ds70083g-page 117 dspic30f 16.2 enabling and setting up uart 16.2.1 enabling the uart the uart module is enabled by setting the uarten bit in the uxmode register (where x = 1 or 2). once enabled, the uxtx and uxrx pins are configured as an output and an input respec tively, overriding the tris and latch register bit se ttings for the corresponding i/o port pins. the uxtx pin is at logic ? 1 ? when no transmission is taking place. 16.2.2 disabling the uart the uart module is disabled by clearing the uarten bit in the uxmode register . this is the default state after any reset. if the uart is disabled, all i/o pins operate as port pins under the control of the latch and tris bits of the corresponding port pins. disabling the uart module re sets the buffers to empty states. any data characters in the buffers are lost and the baud rate counter is reset. all error and status flags associated with the uart module are reset when th e module is disabled. the urxda, oerr, ferr, perr, utxen, utxbrk and utxbf bits are cleared, whereas ridle and trmt are set. other control bits, including adden, urxisel<1:0>, utxisel, as well as the uxmode and uxbrg registers, are not affected. clearing the uarten bit whil e the uart is active will abort all pending transmissio ns and receptions and reset the module as defin ed above. re-enabling the uart will restart the uart in the same configuration. 16.2.3 alternate i/o the alternate i/o function is enabled by setting the altio bit (uxmode<10>). if altio = 1 , the uxatx and uxarx pins (alternate transmit and alternate receive pins, respectively) are used by the uart mod- ule instead of the uxtx and uxrx pins. if altio = 0 , the uxtx and uxrx pins are used by the uart module. 16.2.4 setting up data, parity and stop bit selections control bits pdsel<1:0> in the uxmode register are used to select the data length and parity used in the transmission. the data length may either be 8 bits with even, odd or no parity, or 9 bits with no parity. the stsel bit determines whet her one or two stop bits will be used during data transmission. the default (power-on) setting of the uart is 8 bits, no parity and 1 stop bit (typically represented as 8, n, 1). 16.3 transmitting data 16.3.1 transmitting in 8-bit data mode the following steps must be performed in order to transmit 8-bit data: 1. set up the uart: first, the data length, parity and number of stop bits must be selected. then, the transmit and receive interrupt enable and priority bits are setup in the uxmode and uxsta registers. also, the appropriate baud rate value must be written to the uxbrg register. 2. enable the uart by setting the uarten bit (uxmode<15>). 3. set the utxen bit (uxsta<10>), thereby enabling a transmission. 4. write the byte to be transmitted to the lower byte of uxtxreg. the value wi ll be transferred to the transmit shift register (uxtsr) immediately and the serial bit stream will start shifting out during the next rising e dge of the baud clock. alternatively, the data byte may be written while utxen = 0 , following which, the user may set utxen. this will cause the serial bit stream to begin immediately becaus e the baud clock will start from a cleared state. 5. a transmit interrupt wi ll be generated, depend- ing on the value of the interrupt control bit utxisel (uxsta<15>). 16.3.2 transmitting in 9-bit data mode the sequence of steps involved in the transmission of 9-bit data is similar to 8-bi t transmission, except that a 16-bit data word (of which the upper 7 bits are always clear) must be written to the uxtxreg register. 16.3.3 transmit buffer (u x txb) the transmit buffer is 9 bits wide and 4 characters deep. including the transmit shift register (uxtsr), the user effectively has a 5-deep fifo (first-in, first- out) buffer. the utxbf status bit (uxsta<9>) indicates whether the transmit buffer is full. if a user attempts to write to a full buffer, the new data will not be accepted into the fifo, and no data shift will occur within the buffer. this enables recovery from a buffer overrun condition. the fifo is reset during any device reset but is not affected when the device enters or wakes up from a power saving mode.
dspic30f ds70083g-page 118 preliminary ? 2004 microchip technology inc. 16.3.4 transmit interrupt the transmit interrupt fl ag (u1txif or u2txif) is located in the corresponding interrupt flag register. the transmitter generates an edge to set the uxtxif bit. the condition for gener ating the interrupt depends on the utxisel control bit: a) if utxisel = 0 , an interrupt is generated when a word is transferred from the transmit buffer to the transmit shift register (uxtsr). this implies that the transmit buffer has at least one empty word. b) if utxisel = 1 , an interrupt is generated when a word is transferred from the transmit buffer to the transmit shift register (uxtsr) and the transmit buffer is empty. switching between the two interrupt modes during operation is possible and sometimes offers more flexibility. 16.3.5 transmit break setting the utxbrk bit (u xsta<11>) will cause the uxtx line to be driven to logic ? 0 ?. the utxbrk bit overrides all transmission activity. therefore, the user should generally wait for the transmitter to be idle before setting utxbrk. to send a break character, the utxbrk bit must be set by software and must rema in set for a minimum of 13 baud clock cycles. the utxbrk bit is then cleared by software to generate stop bits. the user must wait for a duration of at least one or two baud clock cycles in order to ensure a valid stop bit(s) before reloading the uxtxb, or starting other transmitter activity. transmis- sion of a break character does not generate a transmit interrupt. 16.4 receiving data 16.4.1 receiving in 8-bit or 9-bit data mode the following steps must be performed while receiving 8-bit or 9-bit data: 1. set up the uart (see section 16.3.1). 2. enable the uart (see section 16.3.1). 3. a receive interrupt will be generated when one or more data words have been received, depending on the receive interrupt settings specified by the urxisel bits (uxsta<7:6>). 4. read the oerr bit to determine if an overrun error has occurred. the oerr bit must be reset in software. 5. read the received data from uxrxreg. the act of reading uxrxreg will move the next word to the top of the receive fifo, and the perr and ferr values will be updated. 16.4.2 receive buffer (u x rxb) the receive buffer is 4 wo rds deep. including the receive shift register (uxrsr), the user effectively has a 5-word deep fifo buffer. urxda (uxsta<0>) = 1 indicates that the receive buffer has data available. urxda = 0 implies that the buffer is empty. if a user attempts to read an empty buffer, the old values in th e buffer will be read and no data shift will occur within the fifo. the fifo is reset during any device reset. it is not affected when the device enters or wakes up from a power saving mode. 16.4.3 receive interrupt the receive interrupt flag (u1rxif or u2rxif) can be read from the corresponding interrupt flag register. the interrupt flag is set by an edge generated by the receiver. the condition for setting the receive interrupt flag depends on the settings specified by the urxisel<1:0> (uxsta<7:6>) control bits. a) if urxisel<1:0> = 00 or 01 , an interrupt is gen- erated every time a data word is transferred from the receive shift register (uxrsr) to the receive buffer. ther e may be one or more characters in the receive buffer. b) if urxisel<1:0> = 10 , an interrupt is generated when a word is transferred from the receive shift register (uxrsr) to the receive buffer, which as a result of the transfer, contains 3 characters. c) if urxisel<1:0> = 11 , an interrupt is set when a word is transferred from the receive shift reg- ister (uxrsr) to the receive buffer, which as a result of the transfer, contains 4 characters (i.e., becomes full). switching between the interrupt modes during opera- tion is possible, though g enerally not ad visable during normal operation. 16.5 reception error handling 16.5.1 receive buffer overrun error (oerr bit) the oerr bit (uxsta<1>) is set if all of the following conditions occur: a) the receive buffer is full. b) the receive shift register is full, but unable to transfer the character to the receive buffer. c) the stop bit of the character in the uxrsr is detected, indicating t hat the uxrsr needs to transfer the character to the buffer. once oerr is set, no further data is shifted in uxrsr (until the oerr bit is cleared in software or a reset occurs). the data held in uxrsr and uxrxreg remains valid.
? 2004 microchip technology inc. preliminary ds70083g-page 119 dspic30f 16.5.2 framing error (ferr) the ferr bit (uxsta<2>) is set if a ? 0 ? is detected instead of a stop bit. if two stop bits are selected, both stop bits must be ? 1 ?, otherwise ferr will be set. the read only ferr bit is buffere d along with the received data. it is cleared on any reset. 16.5.3 parity error (perr) the perr bit (uxsta<3>) is set if the parity of the received word is incorrect. this error bit is applicable only if a parity mode (odd or even) is selected. the read only perr bit is buffere d along with the received data bytes. it is cleared on any reset. 16.5.4 idle status when the receiver is active (i.e., between the initial detection of the start bit and the completion of the stop bit), the ridle bit (uxsta<4>) is ? 0 ?. between the com- pletion of the stop bit and detection of the next start bit, the ridle bit is ? 1 ?, indicating that the uart is idle. 16.5.5 receive break the receiver will count and expect a certain number of bit times based on the va lues programmed in the pdsel (uxmode<2:1>) and stsel (uxmode<0>) bits. if the break is longer than 13 bit times, the reception is considered complete afte r the number of bit times specified by pdsel and st sel. the urxda bit is set, ferr is set, zeros are load ed into the receive fifo, interrupts are generated if appropriate and the ridle bit is set. when the module receives a long break signal and the receiver has detected the start bit, the data bits and the invalid stop bit (which sets the ferr), the receiver must wait for a valid stop bi t before looking for the next start bit. it cannot assume that the break condition on the line is the next start bit. break is regarded as a character containing all ? 0 ?s with the ferr bit set. the break c haracter is loaded into the buffer. no further reception can occur until a stop bit is received. note that ridle goes high when the stop bit has not yet been received. 16.6 address detect mode setting the adden bit (uxs ta<5>) enables this spe- cial mode in which a 9th bit (urx8) value of ? 1 ? identi- fies the received word as an address, rather than data. this mode is only applicable for 9-bit data communica- tion. the urxisel control bit does not have any impact on interrupt generat ion in this mode since an interrupt (if enabled) will be generated every time the received word has the 9th bit set. 16.7 loopback mode setting the lpback bit enables this special mode in which the uxtx pin is intern ally connected to the uxrx pin. when configured for the loopback mode, the uxrx pin is disconnected from the internal uart receive logic. however, the uxtx pin still functions as in a normal operation. to select this mode: a) configure uart for de sired mode of operation. b) set lpback = 1 to enable loopback mode. c) enable transmission as defined in section 16.3. 16.8 baud rate generator the uart has a 16-bit baud rate generator to allow maximum flexibility in baud rate generation. the baud rate generator register (uxbrg) is readable and writable. the baud rate is computed as follows: brg = 16-bit value held in uxbrg register (0 through 65535) f cy = instruction clock rate (1/t cy ) the baud rate is given by equation 16-1. equation 16-1: baud rate therefore, the maximum baud rate possible is f cy /16 (if brg = 0 ), and the minimum baud rate possible is f cy / (16* 65536). with a full 16-bit baud ra te generator at 30 mips operation, the minimum baud rate achievable is 28.5 bps. baud rate = f cy / (16*(brg+1))
dspic30f ds70083g-page 120 preliminary ? 2004 microchip technology inc. 16.9 auto baud support to allow the system to determine baud rates of received characters, the i nput can be optionally linked to a capture input (ic1 for uart1, ic2 for uart2). to enable this mode, the user must program the input cap- ture module to detect the fa lling and rising edges of the start bit. 16.10 uart operation during cpu sleep and idle modes 16.10.1 uart operation during cpu sleep mode when the device enters sleep mode, all clock sources to the module are shutdo wn and stay at logic ? 0 ?. if entry into sleep mode occurs while a transmission is in progress, then the transm ission is aborted. the uxtx pin is driven to logic ? 1 ?. similarly, if entry into sleep mode occurs while a receptio n is in progress, then the reception is aborted. the uxsta, uxmode, transmit and receive registers and buffers, and the uxbrg register are not affected by sleep mode. if the wake bit (uxsta<7>) is set before the device enters sleep mode, then a falling edge on the uxrx pin will generate a receive inte rrupt. the receive interrupt select mode bit (urxisel) has no effect for this func- tion. if the receive interrupt is enabled, then this will wake-up the device from sleep. the uarten bit must be set in order to generate a wake-up interrupt. 16.10.2 uart operation during cpu idle mode for the uart, the usidl bit selects if the module will stop operation when the de vice enters idle mode or whether the module will continue on idle. if usidl = 0 , the module will continue opera tion during idle mode. if usidl = 1 , the module will stop on idle.
? 2004 microchip technology inc. preliminary ds70083g-page 121 dspic30f table 16-1: uart1 register map table 16-2: uart2 register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state u1mode 020c uarten ?usidl ? ?altio ? ? wake lpback abaud ? ? pdsel1 pdsel0 stsel 0000 0000 0000 0000 u1sta 020e utxisel ? ? ? utxbrk utxen utxbf trmt urxisel1 urxis el0 adden ridle perr ferr oerr urxda 0000 0001 0001 0000 u1txreg 0210 ? ? ? ? ? ? ? utx8 transmit register 0000 000u uuuu uuuu u1rxreg 0212 ? ? ? ? ? ? ? urx8 receive register 0000 0000 0000 0000 u1brg 0214 baud rate generator prescaler 0000 0000 0000 0000 legend: u = uninitialized bit sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state u2mode 0216 uarten ?usidl ? ? ? ? ? wake lpback abaud ? ? pdsel1 pdsel0 stsel 0000 0000 0000 0000 u2sta 0218 utxisel ? ? ? utxbrk utxen utxbf trmt urxisel1 urxis el0 adden ridle perr ferr oerr urxda 0000 0001 0001 0000 u2txreg 021a ? ? ? ? ? ? ? utx8 transmit register 0000 000u uuuu uuuu u2rxreg 021c ? ? ? ? ? ? ? urx8 receive register 0000 0000 0000 0000 u2brg 021e baud rate generator prescaler 0000 0000 0000 0000 legend: u = uninitialized bit
dspic30f ds70083g-page 122 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 123 dspic30f 17.0 can module 17.1 overview the controller area network (can) module is a serial interface, useful for communicating with other can modules or microcontroller devices. this interface/ protocol was designed to allow communications within noisy environments. the can module is a communi cation controller imple- menting the can 2.0 a/b protocol, as defined in the bosch specification. the module will support can 1.2, can 2.0a, can 2. 0b passive, and can 2.0b active versions of the protocol. the module implemen- tation is a full can system. the can specification is not covered within this data sheet. the reader may refer to the bosch can specification for further details. the module features are as follows: implementation of the can protocol can 1.2, can 2.0a and can 2.0b standard and extended data frames 0-8 bytes data length programmable bit rate up to 1 mbit/sec support for remote frames double-buffered receiver with two prioritized received message storage buffers (each buffer may contain up to 8 bytes of data) 6 full (standard/extend ed identifier) acceptance filters, 2 associated with the high priority receive buffer and 4 associated with the low priority receive buffer 2 full acceptance fi lter masks, one each associated with the high and low priority receive buffers three transmit buffers with application specified prioritization and abort capability (each buffer may contain up to 8 bytes of data) programmable wake-up functionality with integrated low-pass filter programmable loopback mode supports self-test operation signaling via interrupt capabilities for all can receiver and transmitter error states programmable clock source programmable link to input capture module (ic2, for both can1 and can2) for time-stamping and network synchronization low power sleep and idle mode the can bus module consists of a protocol engine and message buffering/control. the can protocol engine handles all functions for receiving and transmitting messages on the can bus. messages are transmitted by first loading the appropria te data registers. status and errors can be checked by reading the appropriate registers. any message detected on the can bus is checked for errors and then matched against filters to see if it should be received and stored in one of the receive registers. 17.2 frame types the can module transmits various types of frames which include data messages or remote transmission requests initiated by the user, as other frames that are automatically generated for control purposes. the following frame types are supported: standard data frame: a standard data frame is generated by a node when the node wishes to tr ansmit data. it includes an 11-bit standard identifier (sid) but not an 18-bit extended identifier (eid). extended data frame: an extended data frame is similar to a standard data frame but includes an extended identifier as well. remote frame: it is possible for a destin ation node to request the data from the source. for this purpose, the desti- nation node sends a remote frame with an identi- fier that matches the identi fier of the required data frame. the appropriate da ta source node will then send a data frame as a response to this remote request. error frame: an error frame is gene rated by any node that detects a bus error. an er ror frame consists of 2 fields: an error flag fiel d and an error delimiter field. overload frame: an overload frame can be generated by a node as a result of 2 conditions. first, the node detects a dominant bit during interframe space which is an illegal condition. second, due to internal condi- tions, the node is not yet able to start reception of the next message. a n ode may generate a maxi- mum of 2 sequential overload frames to delay the start of the next message. interframe space: interframe space separates a proceeding frame (of whatever type) from a following data or remote frame. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046).
dspic30f ds70083g-page 124 preliminary ? 2004 microchip technology inc. figure 17-1: can buffers and protocol engine block diagram acceptance filter rxf2 r x b 1 a c c e p t a c c e p t identifier data field data field identifier acceptance mask rxm1 acceptance filter rxf3 acceptance filter rxf4 acceptance filter rxf5 m a b acceptance mask rxm0 acceptance filter rxf0 acceptance filter rxf1 r x b 0 msgreq txb2 txabt txlarb txerr mtxbuff message message queue control transmit byte sequencer msgreq txb1 txabt txlarb txerr mtxbuff message msgreq txb0 txabt txlarb txerr mtxbuff message receive shift transmit shift receive error transmit error protocol rerrcnt terrcnt err pas bus off finite state machine counter counter transmit logic bit timing logic citx (1) cirx (1) bit timing generator protocol engine buffers crc check crc generator note 1: i = 1 or 2 refers to a part icular can module (can1 or can2).
? 2004 microchip technology inc. preliminary ds70083g-page 125 dspic30f 17.3 modes of operation the can module can operate in one of several operation modes selected by the user. these modes include: initialization mode disable mode normal operation mode listen only mode loopback mode error recognition mode modes are requested by setting the reqop<2:0> bits (cictrl<10:8>), except the error recognition mode which is requested through the rxm<1:0> bits (cirxncon<6:5>, where n = 0 or 1 represents a par- ticular receive buffer). en try into a mode is acknowl- edged by monitoring the opmode<2:0> bits (cictrl<7:5>). the module will not change the mode and the opmode bits until a change in mode is acceptable, generally during bus idle time which is defined as at least 11 c onsecutive recessive bits. 17.3.1 initialization mode in the initialization mode, th e module will not transmit or receive. the error counters are cleared and the inter- rupt flags remain unch anged. the programmer will have access to configuratio n registers that are access restricted in other modes. the module will protect the user from accidentally vi olating the can protocol through programming errors. all registers which control the configuration of the module can not be modified while the module is on-line. the can module will not be allowed to enter the configuration mode while a transmission is taking place. the configuration mode serves as a lock to prot ect the following registers. all module control registers baud rate and interrupt configuration registers bus timing registers identifier acceptance filter registers identifier acceptance mask registers 17.3.2 disable mode in disable mode, the module will not transmit or receive. the module has the ability to set the wakif bit due to bus activity, however, any pending interrupts will remain and the error counter s will retain their value. if the reqop<2:0> bits (cictrl<10:8>) = 001 , the module will enter the module disable mode. if the module is active, the module will wa it for 11 recessive bits on the can bus, detect that condition as an idle bus, then accept the module disab le command. when the opmode<2:0> bits (cictrl<7:5>) = 001 , that indi- cates whether the module succ essfully went into module disable mode. the i/o pins w ill revert to normal i/o function when the module is in the module disable mode. the module can be program med to apply a low-pass filter function to the cirx input line while the module or the cpu is in sleep mode. the wakfil bit (cicfg2<14>) enables or disables the filter. 17.3.3 normal operation mode normal operating mode is selected when reqop<2:0> = 000 . in this mode, th e module is acti- vated and the i/o pins will assume the can bus func- tions. the module will transmit and receive can bus messages via the cxtx and cxrx pins. 17.3.4 listen only mode if the listen only mode is ac tivated, the module on the can bus is passive. the transmitter buffers revert to the port i/o function. the re ceive pins remain inputs. for the receiver, no error flags or acknowledge signals are sent. the error counter s are deactivated in this state. the listen only mode can be used for detecting the baud rate on the can bus. to use this, it is neces- sary that there are at l east two further nodes that communicate with each other. 17.3.5 listen all messages mode the module can be set to ignore all errors and receive any message. the error recognition mode is activated by setting reqop<2:0> = 111 . in this mode, the data which is in the message asse mbly buffer until the time an error occurred, is copied in the receive buffer and can be read via the cpu interface. 17.3.6 loopback mode if the loopback mode is act ivated, the module will con- nect the internal transmit sig nal to the internal receive signal at the module bo undary. the transmit and receive pins revert to their port i/o function. note: typically, if the can module is allowed to transmit in a particular mode of operation and a transmission is requested immedi- ately after the can module has been placed in that mode of operation, the mod- ule waits for 11 consecutive recessive bits on the bus before starting transmission. if the user switches to disable mode within this 11-bit period, then this transmission is aborted and the corr esponding txabt bit is set and txreq bit is cleared.
dspic30f ds70083g-page 126 preliminary ? 2004 microchip technology inc. 17.4 message reception 17.4.1 receive buffers the can bus module has 3 receive buffers. however, one of the receive buffers is always committed to mon- itoring the bus for incoming messages. this buffer is called the message assembly buffer (mab). so there are 2 receive buffers visible, rxb0 and rxb1, that can essentially instantaneously receive a complete message from the protocol engine. all messages are assembled by the mab and are trans- ferred to the rxbn buffers only if the acceptance filter criterion are met. when a message is received, the rxnif flag (ciintf<0> or ciinrf<1>) will be set. this bit can only be set by the module when a message is received. the bit is cleared by the cpu when it has com- pleted processing the message in the buffer. if the rxnie bit (ciinte<0> or ciinte<1>) is set, an interrupt will be generated when a message is received. rxf0 and rxf1 filters with rxm0 mask are associated with rxb0. the filters rxf2, rxf3, rxf4, and rxf5 and the mask rxm1 are associated with rxb1. 17.4.2 message acceptance filters the message acceptance filt ers and masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buff- ers. once a valid message has been received into the message assembly buffer (mab), the identifier fields of the message are compared to the filter values. if there is a match, that message will be loaded into the appropriate receive buffer. the acceptance filter looks at incoming messages for the rxide bit (cirxnsid< 0>) to determine how to compare the identifiers. if the rxide bit is clear, the message is a standard frame and only filters with the exide bit (cirxfnsid<0>) clear are compared. if the rxide bit is set, the messag e is an extended frame, and only filters with the exide bit set are compared. configuring the rxm<1:0> bits to ? 01 ? or ? 10 ? can override the exide bit. 17.4.3 message acceptance filter masks the mask bits essentially determine which bits to apply the filter to. if any mask bit is set to a zero, then that bit will automatically be accepted regardless of the filter bit. there are 2 programmable acceptance filter masks associated with the receive buffers, one for each buffer. 17.4.4 receive overrun an overrun condition oc curs when the message assembly buffer (mab) has assembled a valid received message, the message is accepted through the acceptance filters, and when the receive buffer associated with the filter has not been designated as clear of the previous message. the overrun error flag, rxnovr (ciintf<15> or ciintf<14>), and the errif bit (ciintf<5>) will be set and the message in th e mab will be discarded. if the dben bit is clear, r xb1 and rxb0 operate inde- pendently. when this is the case, a message intended for rxb0 will not be diverted into rxb1 if rxb0 con- tains an unread message and the rx0ovr bit will be set. if the dben bit is set, the overrun for rxb0 is handled differently. if a valid messag e is received for rxb0 and rxful = 1 indicates that rxb0 is full and rxful = 0 indicates that rxb1 is em pty, the message for rxb0 will be loaded into rxb1. an overrun error will not be generated for rxb0. if a va lid message is received for rxb0 and rxful = 1 , indicating that both rxb0 and rxb1 are full, the message will be lost and an overrun will be indicated for rxb1. 17.4.5 receive errors the can module will detect the following receive errors: cyclic redundancy check (crc) error bit stuffing error invalid message receive error these receive errors do not generate an interrupt. however, the receive error counter is incremented by one in case one of these er rors occur. the rxwar bit (ciintf<9>) indicates that the receive error counter has reached the cpu warning limit of 96 and an interrupt is generated. 17.4.6 receive interrupts receive interrupts can be divided into 3 major groups, each including various cond itions that generate interrupts: receive interrupt: a message has been successfully received and loaded into one of the receive buffers. this inter- rupt is activated immedi ately after receiving the end of frame (eof) field. reading the rxnif flag will indicate which receive buffer caused the interrupt. wake-up interrupt: the can module has wo ken up from disable mode or the device has woken up from sleep mode.
? 2004 microchip technology inc. preliminary ds70083g-page 127 dspic30f receive error interrupts: a receive error interrupt will be indicated by the errif bit. this bit shows that an error condition occurred. the source of the error can be deter- mined by checking the bits in the can interrupt status register, ciintf. - invalid message received: if any type of error occurred during reception of the last message, an er ror will be indicated by the ivrif bit. - receiver overrun: the rxnovr bit indica tes that an overrun condition occurred. - receiver warning: the rxwar bit indicates that the receive error counter (rerrcnt<7:0>) has reached the warning limit of 96. - receiver error passive: the rxep bit indicates that the receive error counter has exceeded the error passive limit of 127 and the module has go ne into error passive state. 17.5 message transmission 17.5.1 transmit buffers the can module has three transmit buffers. each of the three buffers occupies 14 bytes of data. eight of the bytes are the maximum 8 bytes of the transmitted mes- sage. five bytes hold the standard and extended identifiers and other message arbitration information. 17.5.2 transmit message priority transmit priority is a priori tization within each node of the pending transmittabl e messages. there are 4 levels of transmit priority. if txpri<1:0> (citxncon<1:0>, where n = 0, 1 or 2 represents a par- ticular transmit buffer) for a particular message buffer is set to ? 11 ?, that buffer has th e highest priority. if txpri<1:0> for a particular message buffer is set to ? 10 ? or ? 01 ?, that buffer has an intermediate priority. if txpri<1:0> for a particu lar message buffer is ? 00 ?, that buffer has the lowest priority. 17.5.3 transmission sequence to initiate transmission of the message, the txreq bit (citxncon<3>) must be set. the can bus module resolves any timing conflicts between setting of the txreq bit and the start of frame (sof), ensuring that if the priority was changed, it is resolved correctly before the sof occurs. when txreq is set, the txabt (citxncon<6>), txlarb (citxncon<5>) and txerr (citxncon<4>) flag bits are automatically cleared. setting txreq bit simply fl ags a message buffer as enqueued for transmission. when the module detects an available bus, it begi ns transmitting the message which has been determined to have the highest priority. if the transmission completes successfully on the first attempt, the txreq bit is cleared automatically, and an interrupt is generated if txie was set. if the message transmission fa ils, one of the error con- dition flags will be set, and the txreq bit will remain set indicating that the mess age is still pending for trans- mission. if the message encountered an error condition during the transmission atte mpt, the txerr bit will be set, and the error condition may cause an interrupt. if the message loses arbitration during the transmission attempt, the txlarb bit is set. no interrupt is generated to signal the loss of arbitration. 17.5.4 aborting message transmission the system can also abort a message by clearing the txreq bit associated with each message buffer. set- ting the abat bit (cictrl< 12>) will request an abort of all pending messages. if the message has not yet started transmission, or if the message started but is interrupted by loss of arbitr ation or an error, the abort will be processed. the abort is indicated when the module sets the txabt bit and the txnif flag is not automatically set. 17.5.5 transmission errors the can module will detect the following transmission errors: acknowledge error form error bit error these transmission errors wi ll not necessarily generate an interrupt but are indicate d by the transmission error counter. however, each of these errors will cause the transmission error counter to be incremented by one. once the value of the erro r counter exceeds the value of 96, the errif (ciin tf<5>) and the txwar bit (ciintf<10>) are set. once the value of the error counter exceeds the value of 96, an interrupt is generated and the txwar bit in the error flag register is set.
dspic30f ds70083g-page 128 preliminary ? 2004 microchip technology inc. 17.5.6 transmit interrupts transmit interrupts can be di vided into 2 major groups, each including various c onditions that generate interrupts: transmit interrupt: at least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmissio n. reading the txnif flags will indicate which transmit buffer is available and caused the interrupt. transmit error interrupts: a transmission error inte rrupt will be indicated by the errif flag. this flag shows that an error con- dition occurred. the sour ce of the error can be determined by checking t he error flags in the can interrupt status register, ciintf. the flags in this register are related to receive and transmit errors. - transmitter warning interrupt: the txwar bit indicates that the transmit error counter has reached the cpu warning limit of 96. - transmitter error passive: the txep bit (ciintf<12 >) indicates that the transmit error counter has exceeded the error passive limit of 127 and the module has gone to error passive state. - bus off: the txbo bit (ciintf<13>) indicates that the transmit error counter has exceeded 255 and the module has gone to the bus off state. 17.6 baud rate setting all nodes on any particular can bus must have the same nominal bit rate. in orde r to set the baud rate, the following parameters ha ve to be initialized: synchronization jump width baud rate prescaler phase segments length determination of phase segment 2 sample point propagation segment bits 17.6.1 bit timing all controllers on the can bus must have the same baud rate and bit length. howe ver, different controllers are not required to have the same master oscillator clock. at different clock fr equencies of the individual controllers, the baud rate has to be adjusted by adjusting the number of ti me quanta in each segment. the nominal bit time can be thought of as being divided into separate non-overlapping time segments. these segments are shown in figure 17-2. synchronization segment (sync seg) propagation time segment (prop seg) phase segment 1 (phase1 seg) phase segment 2 (phase2 seg) the time segments and also the nominal bit time are made up of integer units of time called time quanta or t q . by definition, the nominal bit time has a minimum of 8 t q and a maximum of 25 t q . also, by definition, the minimum nominal bit time is 1 sec corresponding to a maximum bit rate of 1 mhz. figure 17-2: can bit timing input signal sync prop segment phase segment 1 phase segment 2 sync sample point t q
? 2004 microchip technology inc. preliminary ds70083g-page 129 dspic30f 17.6.2 prescaler setting there is a programmable prescaler with integral values ranging from 1 to 64, in addition to a fixed divide-by-2 for clock generation. the time quantum (t q ) is a fixed unit of time derived from the oscillator period, and is given by equation 17-1, where f can is f cy (if the can- cks bit is set) or 4f cy (if cancks is clear). equation 17-1: time quantum for clock generation 17.6.3 propagation segment this part of the bit time is used to compensate physical delay times within the netw ork. these delay times con- sist of the signal propagation time on the bus line and the internal delay time of the nodes. the prop seg can be programmed from 1 t q to 8 t q by setting the prseg<2:0> bits (cicfg2<2:0>). 17.6.4 phase segments the phase segments are used to optimally locate the sampling of the received bit within the transmitted bit time. the sampling point is between phase1 seg and phase2 seg. these segments are lengthened or short- ened by resynchronization. the end of the phase1 seg determines the sampling poin t within a bit period. the segment is programmable from 1 t q to 8 t q . phase2 seg provides delay to the next transmitted data transi- tion. the segment is programmable from 1 t q to 8 t q , or it may be defined to be equal to the greater of phase1 seg or the information processing time (2 t q ). the phase1 seg is initialized by setting bits seg1ph<2:0> (cicfg2<5:3>), and phase2 seg is initialized by setting seg2ph<2:0> (cicfg2<10:8>). the following requirement mu st be fulfilled while setting the lengths of the phase segments: prop seg + phase1 seg > = phase2 seg 17.6.5 sample point the sample point is the point of time at which the bus level is read and interpreted as the value of that respec- tive bit. the location is at th e end of phase1 seg. if the bit timing is slow an d contains many t q , it is possible to specify multiple sampling of the bus line at the sample point. the level determined by the can bus then corre- sponds to the result from the majority decision of three values. the majority samples are taken at the sample point and twice before with a distance of t q /2. the can module allows the user to choose between sam- pling three times at the same point or once at the same point, by setting or clearing the sam bit (cicfg2<6>). typically, the sampling of the bit should take place at about 60 - 70% through the bit time, depending on the system parameters. 17.6.6 synchronization to compensate for phase sh ifts between the oscillator frequencies of the different bus stations, each can controller must be able to synchronize to the relevant signal edge of the incoming signal. when an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (synchro- nous segment). the circuit wi ll then adjust the values of phase1 seg and phas e2 seg. there are 2 mechanisms used to synchronize. 17.6.6.1 hard synchronization hard synchronization is only done whenever there is a ?recessive? to ?dominant? e dge during bus idle indicating the start of a message. after hard synchronization, the bit time counters are restarted with the sync seg. hard synchronization forces the edge which has caused the hard synchronization to lie within the synchronization segment of the restarted bit time. if a hard synchroniza- tion is done, there will no t be a resynchronization within that bit time. 17.6.6.2 resynchronization as a result of resynchronization, phase1 seg may be lengthened or phase2 seg may be shortened. the amount of lengthening or shortening of the phase buffer segment has an upper bound known as the syn- chronization jump width, and is specified by the sjw<1:0> bits (cicfg1<7:6>). the value of the syn- chronization jump width will be added to phase1 seg or subtracted from phase2 seg. the resynchronization jump width is programmable between 1 t q and 4 t q . the following requirement must be fulfilled while setting the sjw<1:0> bits: phase2 seg > synchronization jump width note: f can must not exceed 30 mhz. if cancks = 0 , then f cy must not exceed 7.5 mhz. t q = 2 (brp<5:0> + 1) / f can
dspic30f ds70083g-page 130 preliminary ? 2004 microchip technology inc. table 17-1: can1 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state c1rxf0sid 0300 ? ? ? receive acceptance filt er 0 standard identifier <10:0> ?exide 000u uuuu uuuu uu0u c1rxf0eidh 0302 ? ? ? ? receive acceptance filter 0 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rxf0eidl 0304 receive acceptance filter 0 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxf1sid 0308 ? ? ? receive acceptance filt er 1 standard identifier <10:0> ?exide 000u uuuu uuuu uu0u c1rxf1eidh 030a ? ? ? ? receive acceptance filter 1 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rxf1eidl 030c receive acceptance filter 1 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxf2sid 0310 ? ? ? receive acceptance filt er 2 standard identifier <10:0> ?exide 000u uuuu uuuu uu0u c1rxf2eidh 0312 ? ? ? ? receive acceptance filter 2 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rxf2eidl 0314 receive acceptance filter 2 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxf3sid 0318 ? ? ? receive acceptance filt er 3 standard identifier <10:0> ?exide 000u uuuu uuuu uu0u c1rxf3eidh 031a ? ? ? ? receive acceptance filter 3 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rxf3eidl 031c receive acceptance filter 3 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxf4sid 0320 ? ? ? receive acceptance filt er 4 standard identifier <10:0> ?exide 000u uuuu uuuu uu0u c1rxf4eidh 0322 ? ? ? ? receive acceptance filter 4 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rxf4eidl 0324 receive acceptance filter 4 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxf5sid 0328 ? ? ? receive acceptance filt er 5 standard identifier <10:0> ?exide 000u uuuu uuuu uu0u c1rxf5eidh 032a ? ? ? ? receive acceptance filter 5 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rxf5eidl 032c receive acceptance filter 5 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxm0sid 0330 ? ? ? receive acceptance mask 0 standard identifier <10:0> ?mide 000u uuuu uuuu uu0u c1rxm0eidh 0332 ? ? ? ? receive acceptance mask 0 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rxm0eidl 0334 receive acceptance mask 0 exte nded identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1rxm1sid 0338 ? ? ? receive acceptance mask 1 standard identifier <10:0> ?mide 000u uuuu uuuu uu0u c1rxm1eidh 033a ? ? ? ? receive acceptance mask 1 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rxm1eidl 033c receive acceptance mask 1 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c1tx2sid 0340 transmit buffer 2 standard identifier <10:6> ? ? ? transmit buffer 2 standard identifier <5:0> srr txide uuuu u000 uuuu uuuu c1tx2eid 0342 transmit buf fer 2 extended identifier <17:14> ? ? ? ? transmit buffer 2 extended identifier <13:6> uuuu 0000 uuuu uuuu c1tx2dlc 0344 transmit buffer 2 exten ded identifier <5:0> txrt r txrb1 txrb0 dlc<3:0> ? ? ? uuuu uuuu uuuu u000 c1tx2b1 0346 transmit buffer 2 byte 1 transmit buffer 2 byte 0 uuuu uuuu uuuu uuuu c1tx2b2 0348 transmit buffer 2 byte 3 transmit buffer 2 byte 2 uuuu uuuu uuuu uuuu c1tx2b3 034a transmit buffer 2 byte 5 transmit buffer 2 byte 4 uuuu uuuu uuuu uuuu c1tx2b4 034c transmit buffer 2 byte 7 transmit buffer 2 byte 6 uuuu uuuu uuuu uuuu c1tx2con 034e ? ? ? ? ? ? ? ? ? txabt txlarb txerr txreq ? txpri<1:0> 0000 0000 0000 0000 c1tx1sid 0350 transmit buffer 1 standard identifier <10:6> ? ? ? transmit buffer 1 standard identifier <5:0> srr txide uuuu u000 uuuu uuuu c1tx1eid 0352 transmit buffer 1 extended identifier <17:14> ? ? ? ? transmit buffer 1 extended identifier <13:6> uuuu 0000 uuuu uuuu c1tx1dlc 0354 transmit buffer 1 exten ded identifier <5:0> txrt r txrb1 txrb0 dlc<3:0> ? ? ? uuuu uuuu uuuu u000 legend: u = uninitialized bit
? 2004 microchip technology inc. preliminary ds70083g-page 131 dspic30f c1tx1b1 0356 transmit buffer 1 byte 1 transmit buffer 1 byte 0 uuuu uuuu uuuu uuuu c1tx1b2 0358 transmit buffer 1 byte 3 transmit buffer 1 byte 2 uuuu uuuu uuuu uuuu c1tx1b3 035a transmit buffer 1 byte 5 transmit buffer 1 byte 4 uuuu uuuu uuuu uuuu c1tx1b4 035c transmit buffer 1 byte 7 transmit buffer 1 byte 6 uuuu uuuu uuuu uuuu c1tx1con 035e ? ? ? ? ? ? ? ? ? txabt txlarb txerr txreq ? txpri<1:0> 0000 0000 0000 0000 c1tx0sid 0360 transmit buffer 0 standard identifier <10:6> ? ? ? transmit buffer 0 standard identifier <5:0> srr txide uuuu u000 uuuu uuuu c1tx0eid 0362 transmit buf fer 0 extended identifier <17:14> ? ? ? ? transmit buffer 0 extended identifier <13:6> uuuu 0000 uuuu uuuu c1tx0dlc 0364 transmit buffer 0 exten ded identifier <5:0> txrt r txrb1 txrb0 dlc<3:0> ? ? ? uuuu uuuu uuuu u000 c1tx0b1 0366 transmit buffer 0 byte 1 transmit buffer 0 byte 0 uuuu uuuu uuuu uuuu c1tx0b2 0368 transmit buffer 0 byte 3 transmit buffer 0 byte 2 uuuu uuuu uuuu uuuu c1tx0b3 036a transmit buffer 0 byte 5 transmit buffer 0 byte 4 uuuu uuuu uuuu uuuu c1tx0b4 036c transmit buffer 0 byte 7 transmit buffer 0 byte 6 uuuu uuuu uuuu uuuu c1tx0con 036e ? ? ? ? ? ? ? ? ? txabt txlarb txerr txreq ? txpri<1:0> 0000 0000 0000 0000 c1rx1sid 0370 ? ? ? receive buffer 1 standa rd identifier <10:0> srr rxide 000u uuuu uuuu uuuu c1rx1eid 0372 ? ? ? ? receive buffer 1 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rx1dlc 0374 receive buffer 1 ex tended identifier <5:0> rxrtr rxrb1 ? ? ? rxrb0 dlc<3:0> uuuu uuuu 000u uuuu c1rx1b1 0376 receive buffer 1 byte 1 receive buffer 1 byte 0 uuuu uuuu uuuu uuuu c1rx1b2 0378 receive buffer 1 byte 3 receive buffer 1 byte 2 uuuu uuuu uuuu uuuu c1rx1b3 037a receive buffer 1 byte 5 receive buffer 1 byte 4 uuuu uuuu uuuu uuuu c1rx1b4 037c receive buffer 1 byte 7 receive buffer 1 byte 6 uuuu uuuu uuuu uuuu c1rx1con 037e ? ? ? ? ? ? ? ?rxful ? ? ? rxrtrro filhit<2:0> 0000 0000 0000 0000 c1rx0sid 0380 ? ? ? receive buffer 0 standa rd identifier <10:0> srr rxide 000u uuuu uuuu uuuu c1rx0eid 0382 ? ? ? ? receive buffer 0 extended identifier <17:6> 0000 uuuu uuuu uuuu c1rx0dlc 0384 receive buffer 0 ex tended identifier <5:0> rxrtr rxrb1 ? ? ? rxrb0 dlc<3:0> uuuu uuuu 000u uuuu c1rx0b1 0386 receive buffer 0 byte 1 receive buffer 0 byte 0 uuuu uuuu uuuu uuuu c1rx0b2 0388 receive buffer 0 byte 3 receive buffer 0 byte 2 uuuu uuuu uuuu uuuu c1rx0b3 038a receive buffer 0 byte 5 receive buffer 0 byte 4 uuuu uuuu uuuu uuuu c1rx0b4 038c receive buffer 0 byte 7 receive buffer 0 byte 6 uuuu uuuu uuuu uuuu c1rx0con 038e ? ? ? ? ? ? ? ?rxful ? ? ? rxrtrro dben jtoff filhit0 0000 0000 0000 0000 c1ctrl 0390 cancap ? csidle abat cancks reqop<2:0> opmode<2:0> ? icode<2:0> ? 0000 0100 1000 0000 c1cfg1 0392 ? ? ? ? ? ? ? ? sjw<1:0> brp<5:0> 0000 0000 0000 0000 c1cfg2 0394 ? wakfil ? ? ? seg2ph<2:0> seg2phts sam seg1ph<2:0> prseg<2:0> 0u00 0uuu uuuu uuuu c1intf 0396 rx0ovr rx1ovr txbo txep rxep txwar rxwar e warn ivrif wakif errif tx2if tx1if tx0if rx1if rx0if 0000 0000 0000 0000 c1inte 0398 ? ? ? ? ? ? ? ? ivrie wakie errie tx2ie tx1ie tx0ie rx1e rx0ie 0000 0000 0000 0000 c1ec 039a transmit error count regis ter receive error count register 0000 0000 0000 0000 table 17-1: can1 register map (continued) sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state legend: u = uninitialized bit
dspic30f ds70083g-page 132 preliminary ? 2004 microchip technology inc. table 17-2: can2 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state c2rxf0sid 03c0 ? ? ? receive acceptance filter 0 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c2rxf0eidh 03c2 ? ? ? ? receive acceptance filter 0 extended identifier <17:6> 0000 uuuu uuuu uuuu c2rxf0eidl 03c4 receive acceptance filter 0 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c2rxf1sid 03c8 ? ? ? receive acceptance filter 1 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c2rxf1eidh 03ca ? ? ? ? receive acceptance filter 1 extended identifier <17:6> 0000 uuuu uuuu uuuu c2rxf1eidl 03cc receive acceptance filter 1 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c2rxf2sid 03d0 ? ? ? receive acceptance filter 2 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c2rxf2eidh 03d2 ? ? ? ? receive acceptance filter 2 extended identifier <17:6> 0000 uuuu uuuu uuuu c2rxf2eidl 03d4 receive acceptance filter 2 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c2rxf3sid 03d8 ? ? ? receive acceptance filter 3 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c2rxf3eidh 03da ? ? ? ? receive acceptance filter 3 extended identifier <17:6> 0000 uuuu uuuu uuuu c2rxf3eidl 03dc receive acceptance filter 3 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c2rxf4sid 03e0 ? ? ? receive acceptance filter 4 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c2rxf4eidh 03e2 ? ? ? ? receive acceptance filter 4 extended identifier <17:6> 0000 uuuu uuuu uuuu c2rxf4eidl 03e4 receive acceptance filter 4 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c2rxf5sid 03e8 ? ? ? receive acceptance filter 5 standard identifier <10:0> ? exide 000u uuuu uuuu uu0u c2rxf5eidh 03ea ? ? ? ? receive acceptance filter 5 extended identifier <17:6> 0000 uuuu uuuu uuuu c2rxf5eidl 03ec receive acceptance filter 5 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c2rxm0sid 03f0 ? ? ? receive acceptance mask 0 standard identifier <10:0> ?mide 000u uuuu uuuu uu0u c2rxm0eidh 03f2 ? ? ? ? receive acceptance mask 0 extended identifier <17:6> 0000 uuuu uuuu uuuu c2rxm0eidl 03f4 receive acceptance mask 0 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c2rxm1sid 03f8 ? ? ? receive acceptance mask 1 standard identifier <10:0> ?mide 000u uuuu uuuu uu0u c2rxm1eidh 03fa ? ? ? ? receive acceptance mask 1 extended identifier <17:6> 0000 uuuu uuuu uuuu c2rxm1eidl 03fc receive acceptance mask 1 extended identifier <5:0> ? ? ? ? ? ? ? ? ? ? uuuu uu00 0000 0000 c2tx2sid 0400 transmit buffer 2 standard identifier <10:6> ? ? ? transmit buffer 2 standard identifier <5:0> srr txide uuuu u000 uuuu uuuu c2tx2eid 0402 transmit buffer 2 extended identifier <17:14> ? ? ? ? transmit buffer 2 extended identifier <13:6> uuuu 0000 uuuu uuuu c2tx2dlc 0404 transmit buffer 2 extended identifier <5:0> txrtr txrb1 txrb0 dlc<3:0> ? ? ? uuuu uuuu uuuu u000 c2tx2b1 0406 transmit buffer 2 byte 1 transmit buffer 2 byte 0 uuuu uuuu uuuu uuuu c2tx2b2 0408 transmit buffer 2 byte 3 transmit buffer 2 byte 2 uuuu uuuu uuuu uuuu c2tx2b3 040a transmit buffer 2 byte 5 transmit buffer 2 byte 4 uuuu uuuu uuuu uuuu c2tx2b4 040c transmit buffer 2 byte 7 transmit buffer 2 byte 6 uuuu uuuu uuuu uuuu c2tx2con 040e ? ? ? ? ? ? ? ? ? txabt txlarb txerr txreq ? txpri<1:0> 0000 0000 0000 0000 c2tx1sid 0410 transmit buffer 1 standard identifier <10:6> ? ? ? transmit buffer 1 standard identifier <5:0> srr txide uuuu u000 uuuu uuuu c2tx1eid 0412 transmit buffer 1 extended identifier <17:14> ? ? ? ? transmit buffer 1 extended identifier <13:6> uuuu 0000 uuuu uuuu c2tx1dlc 0414 transmit buffer 1 extended identifier <5:0> txrtr txrb1 txrb0 dlc<3:0> ? ? ? uuuu uuuu uuuu u000 legend: u = uninitialized bit
? 2004 microchip technology inc. preliminary ds70083g-page 133 dspic30f note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. c2tx1b1 0416 transmit buffer 1 byte 1 transmit buffer 1 byte 0 uuuu uuuu uuuu uuuu c2tx1b2 0418 transmit buffer 1 byte 3 transmit buffer 1 byte 2 uuuu uuuu uuuu uuuu c2tx1b3 041a transmit buffer 1 byte 5 transmit buffer 1 byte 4 uuuu uuuu uuuu uuuu c2tx1b4 041c transmit buffer 1 byte 7 transmit buffer 1 byte 6 uuuu uuuu uuuu uuuu c2tx1con 041e ? ? ? ? ? ? ? ? ? txabt txlarb txerr txreq ? txpri<1:0> 0000 0000 0000 0000 c2tx0sid 0420 transmit buffer 0 standard identifier <10:6> ? ? ? transmit buffer 0 standard identifier <5:0> srr txide uuuu u000 uuuu uuuu c2tx0eid 0422 transmit buffer 0 extended identifier <17:14> ? ? ? ? transmit buffer 0 extended identifier <13:6> uuuu 0000 uuuu uuuu c2tx0dlc 0424 transmit buffer 0 extended identifier <5:0> txrtr txrb1 txrb0 dlc<3:0> ? ? ? uuuu uuuu uuuu u000 c2tx0b1 0426 transmit buffer 0 byte 1 transmit buffer 0 byte 0 uuuu uuuu uuuu uuuu c2tx0b2 0428 transmit buffer 0 byte 3 transmit buffer 0 byte 2 uuuu uuuu uuuu uuuu c2tx0b3 042a transmit buffer 0 byte 5 transmit buffer 0 byte 4 uuuu uuuu uuuu uuuu c2tx0b4 042c transmit buffer 0 byte 7 transmit buffer 0 byte 6 uuuu uuuu uuuu uuuu c2tx0con 042e ? ? ? ? ? ? ? ? ? txabt txlarb txerr txreq ? txpri<1:0> 0000 0000 0000 0000 c2rx1sid 0430 ? ? ? receive buffer 1 standard identifier <10:0> srr rxide 000u uuuu uuuu uuuu c2rx1eid 0432 ? ? ? ? receive buffer 1 extended identifier <17:6> 0000 uuuu uuuu uuuu c2rx1dlc 0434 receive buffer 1 ext ended identifier <5:0> rxrtr rxrb1 ? ? ? rxrb0 dlc<3:0> uuuu uuuu 000u uuuu c2rx1b1 0436 receive buffer 1 byte 1 receive buffer 1 byte 0 uuuu uuuu uuuu uuuu c2rx1b2 0438 receive buffer 1 byte 3 receive buffer 1 byte 2 uuuu uuuu uuuu uuuu c2rx1b3 043a receive buffer 1 byte 5 receive buffer 1 byte 4 uuuu uuuu uuuu uuuu c2rx1b4 043c receive buffer 1 byte 7 receive buffer 1 byte 6 uuuu uuuu uuuu uuuu c2rx1con 043e ? ? ? ? ? ? ? ?rxful ? ? ? rxrtrro filhit<2:0> 0000 0000 0000 0000 c2rx0sid 0440 ? ? ? receive buffer 0 standard identifier <10:0> srr rxide 000u uuuu uuuu uuuu c2rx0eid 0442 ? ? ? ? receive buffer 0 extended identifier <17:6> 0000 uuuu uuuu uuuu c2rx0dlc 0444 receive buffer 0 ext ended identifier <5:0> rxrtr rxrb1 ? ? ? rxrb0 dlc<3:0> uuuu uuuu 000u uuuu c2rx0b1 0446 receive buffer 0 byte 1 receive buffer 0 byte 0 uuuu uuuu uuuu uuuu c2rx0b2 0448 receive buffer 0 byte 3 receive buffer 0 byte 2 uuuu uuuu uuuu uuuu c2rx0b3 044a receive buffer 0 byte 5 receive buffer 0 byte 4 uuuu uuuu uuuu uuuu c2rx0b4 044c receive buffer 0 byte 7 receive buffer 0 byte 6 uuuu uuuu uuuu uuuu c2rx0con 044e ? ? ? ? ? ? ? ?rxful ? ? ? rxrtrro dben jtoff filhit0 0000 0000 0000 0000 c2ctrl 0450 cancap ? csidle abat cancks reqop<2:0> opmode<2:0> ? icode<2:0> ? 0000 0100 1000 0000 c2cfg1 0452 ? ? ? ? ? ? ? ? sjw<1:0> brp<5:0> 0000 0000 0000 0000 c2cfg2 0454 ? wakfil ? ? ? seg2ph<2:0> seg2phts sam seg1ph<2:0> prseg<2:0> 0u00 0uuu uuuu uuuu c2intf 0456 rx0ovr rx1ovr txbo txep rxep txwar rxwar ewarn ivrif wakif errif tx2if tx1if tx0if rx1if rx0if 0000 0000 0000 0000 c2inte 0458 ? ? ? ? ? ? ? ? ivrie wakie errie tx2ie tx1ie tx0ie rx1e rx0ie 0000 0000 0000 0000 c2ec 045a transmit error count regi ster receive error count register 0000 0000 0000 0000 table 17-2: can2 register map (continued) sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state legend: u = uninitialized bit
dspic30f ds70083g-page 134 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 135 dspic30f 18.0 data converter interface (dci) module 18.1 module introduction the dspic30f data converter interface (dci) module allows simple interfacing of devices, such as audio coder/decoders (codecs), a/d converters and d/a converters. the following interfaces are supported: framed synchronous serial transfer (single or multi-channel) inter-ic sound (i 2 s) interface ac-link compliant mode the dci module provides the following general features: programmable word size up to 16 bits support for up to 16 time slots, for a maximum frame size of 256 bits data buffering for up to 4 samples without cpu overhead 18.2 module i/o pins there are four i/o pins associated with the module. when enabled, the module cont rols the data direction of each of the four pins. 18.2.1 csck pin the csck pin provides t he serial clock for the dci module. the csck pin may be configured as an input or output using the csckd control bit in the dcicon2 sfr. when configured as an output, the serial clock is provided by the dspic30f. when configured as an input, the serial clock must be provided by an external device. 18.2.2 csdo pin the serial data output (csdo) pin is configured as an output only pin when the module is enabled. the csdo pin drives the serial bus whenever data is to be transmitted. the csdo pin is tri-stated or driven to ? 0 ? during csck periods when data is not transmitted, depending on the state of the csdom control bit. this allows other devices to plac e data on the serial bus during transmission periods not used by the dci module. 18.2.3 csdi pin the serial data input (csd i) pin is configured as an input only pin when th e module is enabled. 18.2.3.1 cofs pin the codec frame synchronization (cofs) pin is used to synchronize data transfers that occur on the csdo and csdi pins. the cofs pi n may be configured as an input or an output. the data direction for the cofs pin is determined by the co fsd control bit in the dcicon1 register. the dci module accesses th e shadow registers while the cpu is in the process of accessing the memory mapped buffer registers. 18.2.4 buffer data alignment data values are always stored left justified in the buff- ers since most codec data is represented as a signed 2?s complement fractional number. if the received word length is less than 16 bits, th e unused ls bits in the receive buffer registers are set to ? 0 ? by the module. if the transmitted word length is less than 16 bits, the unused ls bits in the transmit buffer register are ignored by the module. t he word length setup is described in subsequent se ctions of this document. 18.2.5 transmit/receive shift register the dci module has a 16-bit shift register for shifting serial data in and out of th e module. data is shifted in/ out of the shift register ms bit first, since audio pcm data is transmitted in signed 2?s complement format. 18.2.6 dci buffer control the dci module contains a buffer control unit for trans- ferring data between the shadow buffer memory and the serial shift register. the buffer control unit is a sim- ple 2-bit address counter that points to word locations in the shadow buffer memory. for the receive memory space (high address portion of dci buffer memory), the address counter is concatenated with a ? 0 ? in the msb location to form a 3-bit add ress. for the transmit mem- ory space (high portion of dci buffer memory), the address counter is concatenated with a ? 1 ? in the msb location. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: the dci buffer control unit always accesses the same relative location in the transmit and receive buffers, so only one address counter is provided.
dspic30f ds70083g-page 136 preliminary ? 2004 microchip technology inc. figure 18-1: dci module block diagram bcg control bits 16-bit data bus sample rate generator sckd fsd dci buffer frame synchronization generator control unit dci shift register receive buffer registers w/shadow f osc /4 word size selection bits frame length selection bits dci mode selection bits csck cofs csdi csdo 15 0 transmit buffer registers w/shadow
? 2004 microchip technology inc. preliminary ds70083g-page 137 dspic30f 18.3 dci module operation 18.3.1 module enable the dci module is enabled or disabled by setting/ clearing the dcien control bit in the dcicon1 sfr. clearing the dcien control bi t has the effect of reset- ting the module. in particul ar, all counters associated with csck generation, fram e sync, and the dci buffer control unit are reset. the dci clocks are shutdown when the dcien bit is cleared. when enabled, the dci controls the data direction for the four i/o pins associated with the module. the port, lat and tris register values for these i/o pins are overridden by the dci module when the dcien bit is set. it is also possible to overri de the csck pin separately when the bit clock generato r is enabled. this permits the bit clock generator to operate without enabling the rest of the dci module. 18.3.2 word size selection bits the ws<3:0> word size selection bits in the dcicon2 sfr determine the number of bits in each dci data word. essentially, the ws<3:0> bits determine the counting period for a 4-bit counter clocked from the csck signal. any data length, up to 16-bits, may be selected. the value loaded into the ws<3:0> bits is one less the desired word length. for example, a 16-bit data word size is selected when ws<3:0> = 1111 . 18.3.3 frame sync generator the frame sync generator (cofsg) is a 4-bit counter that sets the frame length in data words. the frame sync generator is incremente d each time the word size counter is reset (refer to se ction 18.3.2). the period for the frame synchronization ge nerator is set by writing the cofsg<3:0> control bits in the dcicon2 sfr. the cofsg period in clock cycles is determined by the following formula: equation 18-1: cofsg period frame lengths, up to 16 data words, may be selected. the frame length in csck periods can vary up to a maximum of 256 depending on the word size that is selected. 18.3.4 frame sync mode control bits the type of frame sync signal is selected using the frame synchronization mode control bits (cofsm<1:0>) in the dcicon1 sfr. the following operating modes can be selected: multi-channel mode i 2 s mode ac-link mode (16-bit) ac-link mode (20-bit) the operation of the cofs m control bits depends on whether the dci module generates the frame sync signal as a master device, or receives the frame sync signal as a slave device. the master device in a dsp/codec pair is the device that generates the frame sync signal. the frame sync signal initiates data transfe rs on the csdi and csdo pins and usually has the sa me frequency as the data sample rate (cofs). the dci module is a frame sync master if the cofsd control bit is cleared and is a frame sync slave if the cofsd control bit is set. 18.3.5 master frame sync operation when the dci module is operating as a frame sync master device (cofsd = 0 ), the cofsm mode bits determine the type of frame sync pulse that is generated by the frame sync generator logic. a new cofs signal is generated when the frame sync generator resets to ? 0 ?. in the multi-channel mode , the frame sync pulse is driven high for the csck period to initiate a data trans- fer. the number of csck cycles between successive frame sync pulses will de pend on the word size and frame sync generator control bits. a timing diagram for the frame sync signal in multi-channel mode is shown in figure 18-2. in the ac-link mode of ope ration, the frame sync sig- nal has a fixed period a nd duty cycle. the ac-link frame sync signal is high fo r 16 csck cycles and is low for 240 csck cycles. a timi ng diagram with the timing details at the start of an ac-link frame is shown in figure 18-3. in the i 2 s mode, a frame sync signal having a 50% duty cycle is generated. the period of the i 2 s frame sync signal in csck cycles is de termined by the word size and frame sync generator control bits. a new i 2 s data transfer boundary is marked by a high-to-low or a low-to-high transition edge on the cofs pin. note: these ws<3:0> control bits are used only in the multi-channel and i 2 s modes. these bits have no effect in ac-link mode since the data slot sizes are fixed by the protocol. note: the cofsg control bits will have no effect in ac-link mode since the frame length is set to 256 csck periods by the protocol. frame length = word length (fsg value + 1)
dspic30f ds70083g-page 138 preliminary ? 2004 microchip technology inc. 18.3.6 slave frame sync operation when the dci module is operating as a frame sync slave (cofsd = 1 ), data transfers are controlled by the codec device attached to the dci module. the cofsm control bits control how the dci module responds to incoming cofs signals. in the multi-channel mode , a new data frame transfer will begin one csck cycle after the cofs pin is sam- pled high (see figure 18- 2). the pulse on the cofs pin resets the frame sync generator logic. in the i 2 s mode, a new data word will be transferred one csck cycle after a low- to-high or a high-to-low transition is sampled on the cofs pin. a rising or fall- ing edge on the cofs pi n resets the frame sync generator logic. in the ac-link mode, the tag slot and subsequent data slots for the next frame w ill be transferred one csck cycle after the cofs pin is sampled high. the cofsg and ws bits mu st be configured to pro- vide the proper frame length when the module is oper- ating in the slave mode. on ce a valid frame sync pulse has been sampled by the module on the cofs pin, an entire data frame transfer will take place. the module will not respond to further frame sync pulses until the data frame transfer has completed. figure 18-2: frame sync timing, multi-channel mode figure 18-3: frame sync timing, ac-link start of frame figure 18-4: i 2 s interface frame sync timing csck csdi/csdo cofs msb lsb ta g msb bit_clk csdo or csdi sync ta g bit 14 s12 lsb s12 bit 1 s12 bit 2 ta g bit 13 msb lsb msb lsb csck csdi or csdo ws note: a 5-bit transfer is shown here for illustration purposes. the i 2 s protocol does not specify word length - this will be system dependent.
? 2004 microchip technology inc. preliminary ds70083g-page 139 dspic30f 18.3.7 bit clock generator the dci module has a dedicated 12-bit time base that produces the bit clock. the bi t clock rate (period) is set by writing a non-zero 12-bit value to the bcg<11:0> control bits in the dcicon1 sfr. when the bcg<11:0> bits are set to zero, the bit clock will be disabled. if the bcg< 11:0> bits are set to a non- zero value, the bit clock generator is enabled. these bits should be set to ? 0 ? and the csckd bit set to ? 1 ? if the serial clock for the dci is received from an external device. the formula for the bit clock frequency is given in equation 18-2. equation 18-2: bit clock frequency the required bit clock frequ ency will be determined by the system sampling rate and frame size. typical bit clock frequencies range from 16x to 512x the converter sample rate depending on the data converter and the communication protocol that is used. to achieve bit clock frequen cies associated with com- mon audio sampling rates, th e user will need to select a crystal frequency that has an ?even? binary value. examples of such crystal frequencies are listed in table 18-1. table 18-1: device frequencies for common codec csck frequencies 18.3.8 sample clock edge control bit the sample clock edge (cscke) control bit determines the sampling edge for the csck signal. if the csck bit is cleared (default), data will be sampled on the falling edge of the csck signal. the ac-link protocols and most multi-channel formats require that data be sam- pled on the falling edge of the csck signal. if the csck bit is set, data will be sampled on the rising edge of csck. the i 2 s protocol requires that data be sampled on the rising edge of the csck signal. 18.3.9 data justification control bit in most applications, the data transfer begins one csck cycle after the cofs signal is sampled active. this is the default configuration of the dci module. an alternate data alignment can be selected by setting the djst control bit in the dcicon2 sfr. when djst = 1 , data transfers will begin during the same csck cycle when the cofs signal is sampled active. 18.3.10 transmit slot enable bits the tscon sfr has control bits that are used to enable up to 16 time slots for transmission. these con- trol bits are the tse<15:0> bits. the size of each time slot is determined by the ws<3:0> word size selection bits and can vary up to 16 bits. if a transmit time slot is enabled via one of the tse bits (tsex = 1 ), the contents of the current transmit shadow buffer location will be loaded into the csdo shift regis- ter and the dci buffer control unit is incremented to point to the next location. during an unused transmit time slot, the csdo pin will drive ? 0 ?s or will be tri-stated during all disabled time slots depending on the stat e of the csdom bit in the dcicon1 sfr. the data frame size in bits is determined by the chosen data word size and the number of data word elements in the frame. if the chosen frame size has less than 16 elements, the additional slo t enable bits will have no effect. each transmit data word is written to the 16-bit transmit buffer as left justified data. if the selected word size is less than 16 bits, then the ls bits of the transmit buffer memory will have no effect on the transmitted data. the user should write ? 0 ?s to the unused ls bits of each transmit buffer location. f osc pll f cyc 2.048 mhz 16x 32.768 mips 4.096 mhz 8x 32.768 mips 4.800 mhz 8x 38.4 mips 9.600 mhz 4x 38.4 mips note 1: when the csck signa l is applied exter- nally (csckd = 1 ), the bcg<11:0> bits have no effect on the operation of the dci module. 2: when the csck signa l is applied exter- nally (csckd = 1 ), the external clock high and low times must meet the device timing requirements. f bck = f cy 2 (bcg + 1)
dspic30f ds70083g-page 140 preliminary ? 2004 microchip technology inc. 18.3.11 receive slot enable bits the rscon sfr contains control bits that are used to enable up to 16 time slots for reception. these control bits are the rse<15:0> bits . the size of each receive time slot is determined by the ws<3:0> word size selection bits and can va ry from 1 to 16 bits. if a receive time slot is enab led via one of the rse bits (rsex = 1 ), the shift register co ntents will be written to the current dci receive shadow buffer location and the buffer control unit will be incremented to point to the next buffer location. data is not packed in the re ceive memory buffer loca- tions if the selected word size is less than 16 bits. each received slot data word is stored in a separate 16-bit buffer location. data is always stored in a left justified format in the receive memory buffer. 18.3.12 slot enable bits operation with frame sync the tse and rse control bits operate in concert with the dci frame sync generator . in the master mode, a cofs signal is generated whenever the frame sync generator is reset. in the slave mode, the frame sync generator is reset whenever a cofs pulse is received. the tse and rse control bits allow up to 16 consecu- tive time slots to be enabled for transmit or receive. after the last enabled time slot has been transmitted/ received, the dci will stop buffering data until the next occurring cofs pulse. 18.3.13 synchronous data transfers the dci buffer control unit will be incremented by one word location whenever a given time slot has been enabled for transmission or reception. in most cases, data input and output trans fers will be synchronized, which means that a data sample is received for a given channel at the same time a data sample is transmitted. therefore, the transmit and re ceive buffers will be filled with equal amounts of data when a dci interrupt is generated. in some cases, the amount of data transmitted and received during a data frame may not be equal. as an example, assume a two-word data frame is used. fur- thermore, assume that da ta is only received during slot #0 but is transmitted du ring slot #0 and slot #1. in this case, the buffer control unit counter would be incre- mented twice during a data frame but only one receive register location woul d be filled with data. 18.3.14 buffer length control the amount of data that is buffered between interrupts is determined by the buffer length (blen<1:0>) control bits in the dcistat sfr. the size of the transmit and receive buffers may be varied from 1 to 4 data words using the blen control bits. the blen control bits are compared to the current value of the dci buffer control unit address counter. when the 2 ls bits of the dci address counter match th e blen<1:0> value, the buffer control unit will be reset to ? 0 ?. in addition, the contents of the receive sh adow registers are trans- ferred to the receive buffer registers and the contents of the transmit buffer registers are transferred to the transmit shadow registers. 18.3.15 buffer alignment with data frames there is no direct coupling between the position of the agu address pointer and t he data frame boundaries. this means that there will be an implied assignment of each transmit and receive buffer that is a function of the blen control bits and the number of enabled data slots via the tse and rse control bits. as an example, assume that a 4-word data frame is chosen and that we want to transmit on all four time slots in the frame. this configuration would be estab- lished by setting the ts e0, tse1, tse2, and tse3 control bits in the tscon sfr. with this module setup, the txbuf0 register woul d be naturally assigned to slot #0, the txbuf1 register would be naturally assigned to slot #1, and so on. note: when more than four time slots are active within a data frame, the user code must keep track of which time slots are to be read/written at each interrupt. in some cases, the alignment between transmit/ receive buffers and their respective slot assignments could be lost. examples of such cases include an emulation break- point or a hardware trap. in these situa- tions, the user should poll the slot status bits to determine what data should be loaded into the buffer registers to resynchronize the software with the dci module.
? 2004 microchip technology inc. preliminary ds70083g-page 141 dspic30f 18.3.16 transmit status bits there are two transmit status bits in the dcistat sfr. the tmpty bit is set when the contents of the transmit buffer registers are transfe rred to the transmit shadow registers. the tmpty bit may be polled in software to determine when the transmit buffer registers may be written. the tmpty bit is cleared automatically by the hardware when a write to one of the four transmit buffers occurs. the tunf bit is read only and indicates that a transmit underflow has occurred for at least one of the transmit buffer registers that is in use. the tunf bit is set at the time the transmit buffer registers are transferred to the transmit shadow registers. the tunf status bit is cleared automatically when th e buffer register that underflowed is written by the cpu. 18.3.17 receive status bits there are two receive status bits in the dcistat sfr. the rful status bit is read only and indicates that new data is available in the receive buffers. the rful bit is cleared automatically when a ll receive buffers in use have been read by the cpu. the rov status bit is read only and indicates that a receive overflow has occurred for at least one of the receive buffer locations. a receive overflow occurs when the buffer location is not read by the cpu before new data is transferred from the shadow registers. the rov status bit is cleared automatically when the buffer register that caused the overflow is read by the cpu. when a receive overflow occurs for a specific buffer location, the old contents of the buffer are overwritten. 18.3.18 slot status bits the slot<3:0> status bits in the dcistat sfr indi- cate the current active time slot. these bits will corre- spond to the value of the fr ame sync generator counter. the user may poll these stat us bits in software when a dci interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the txbuf registers. 18.3.19 csdo mode bit the csdom control bit controls the behavior of the csdo pin during unused trans mit slots. a given trans- mit time slot is unused if it?s corresponding tsex bit in the tscon sfr is cleared. if the csdom bit is cleared (default), the csdo pin will be low during unused time slot periods. this mode will be used when there are only two devices attached to the serial bus. if the csdom bit is set, the csdo pin will be tri-stated during unused time slot period s. this mode allows mul- tiple devices to share the same csdo line in a multi- channel application. each device on the csdo line is configured so that it wi ll only transmit data during specific time slots. no two devices will transmit data during the same time slot. 18.3.20 digital loopback mode digital loopback mode is enabled by setting the dloop control bit in the dcistat sfr. when the dloop bit is set, the module internally connects the csdo signal to csdi. the actual data input on the csdi i/o pin will be ignor ed in digital loopback mode. 18.3.21 underflow mode control bit when an underflow occurs, one of two actions may occur depending on the stat e of the underflow mode (unfm) control bit in the dcicon2 sfr. if the unfm bit is cleared (default), th e module will transmit ? 0 ?s on the csdo pin during the active time slot for the buffer location. in this operat ing mode, the codec device attached to the dci module will simply be fed digital ?silence?. if the unfm control bit is set, the module will transmit the last data written to the buffer location. this operating mode permits the user to send continuous data to the codec device without consuming cpu overhead. 18.4 dci module interrupts the frequency of dci module interrupts is dependent on the blen<1:0> control bits in the dcicon2 sfr. an interrupt to the cpu is generated each time the set buffer length has been reach ed and a shadow register transfer takes place. a shadow register transfer is defined as the time when the previously written txbuf values are transferred to th e transmit shadow registers and new received values in the receive shadow registers are transferred into the rxbuf registers. note: the transmit status bits only indicate sta- tus for buffer locations that are used by the module. if the buffer length is set to less than four words, for example, the unused buffer locations will not affect the transmit status bits. note: the receive status bits only indicate status for buffer locations that are used by the module. if the buffer length is set to less than four words, for example, the unused buffer locations will not affect the transmit status bits.
dspic30f ds70083g-page 142 preliminary ? 2004 microchip technology inc. 18.5 dci module operation during cpu sleep and idle modes 18.5.1 dci module operation during cpu sleep mode the dci module has the abi lity to operate while in sleep mode and wake the cpu when the csck signal is supplied by an external device (csckd = 1 ). the dci module will generate an asynchronous interrupt when a dci buffer transfer has completed and the cpu is in sleep mode. 18.5.2 dci module operation during cpu idle mode if the dcisidl control bit is cleared (default), the mod- ule will continue to operat e normally even in idle mode. if the dcisidl bit is set, the module will halt when idle mode is asserted. 18.6 ac-link mode operation the ac-link protocol is a 25 6-bit frame with one 16-bit data slot, followed by twelve 20-bit data slots. the dci module has two operating modes for the ac-link pro- tocol. these operating modes are selected by the cofsm<1:0> control bits in the dcicon1 sfr. the first ac-link mode is called ?16-bit ac-link mode? and is selected by setting cofsm<1:0> = 10 . the second ac-link mode is called ?20-bit ac-link mode? and is selected by setting cofsm<1:0> = 11 . 18.6.1 16-bit ac-link mode in the 16-bit ac-link mo de, data word lengths are restricted to 16 bits. note that this restriction only affects the 20-bit data time slots of the ac-link proto- col. for received time slot s, the incoming data is simply truncated to 16 bits. for outgoing time slots, the 4 ls bits of the data word are set to ? 0 ? by the module. this truncation of the time slots limits the a/d and dac data to 16 bits but permits pro per data alignment in the txbuf and rxbuf regist ers. each rxbuf and txbuf register will contai n one data time slot value. 18.6.2 20-bit ac-link mode the 20-bit ac-link mode allo ws all bits in the data time slots to be transmitted and re ceived but does not main- tain data alignment in the txbuf and rxbuf registers. the 20-bit ac-link mode functions similar to the multi- channel mode of the dci m odule, except for the duty cycle of the frame synchron ization signal. the ac-link frame synchronization signal sh ould remain high for 16 csck cycles and should be low for the following 240 cycles. the 20-bit mode treats each 256-bit ac-link frame as sixteen, 16-bit time slots. in the 20-bit ac-link mode, the module operates as if cofsg<3:0> = 1111 and ws<3:0> = 1111 . the data alignment for 20-bit data slots is ignored. for exampl e, an entire ac-link data frame can be transmitted and received in a packed fashion by setting all bits in the tscon and rscon sfrs. since the total availabl e buffer length is 64 bits, it would take 4 consecutive interrupts to transfer the ac-link frame. the application software must keep track of the current ac-link frame segment. 18.7 i 2 s mode operation the dci module is configured for i 2 s mode by writing a value of ? 01 ? to the cofsm<1:0> control bits in the dcicon1 sfr. when operating in the i 2 s mode, the dci module will generate frame synchronization sig- nals with a 50% duty cycle. each edge of the frame synchronization signal ma rks the boundary of a new data word transfer. the user must also select the frame length and data word size using the cofsg and ws control bits in the dcicon2 sfr. 18.7.1 i 2 s frame and data word length selection the ws and cofsg control bi ts are set to produce the period for one half of an i 2 s data frame. that is, the frame length is the total number of csck cycles required for a left or a right data word transfer. the blen bits must be set fo r the desired buffer length. setting blen<1:0> = 01 will produce a cpu interrupt, once per i 2 s frame. 18.7.2 i 2 s data justification as per the i 2 s specification, a data word transfer will, by default, begin one csck cycle after a transition of the ws signal. a ?ms bit left justified? option can be selected using the djst control bit in the dcicon2 sfr. if djst = 1 , the i 2 s data transfers will be ms bit left jus- tified. the ms bit of the da ta word will be presented on the csdo pin during the sa me csck cycle as the ris- ing or falling edge of the cofs signal. the csdo pin is tri-stated after the data word has been sent.
? 2004 microchip technology inc. preliminary ds70083g-page 143 dspic30f table 18-2: dci register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bi t 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reset state dcicon1 0240 dcien ? dcisidl ? dloop csckd cscke cofsd unfm csdom djst ? ? ? cofsm1 cofsm0 0000 0000 0000 0000 dcicon2 0242 ? ? ? ? blen1 blen0 ? cofsg<3:0> ? ws<3:0> 0000 0000 0000 0000 dcicon3 0244 ? ? ? ? bcg<11:0> 0000 0000 0000 0000 dcistat 0246 ? ? ? ? slot3 slot2 slot1 slot0 ? ? ? ? rov rful tunf tmpty 0000 0000 0000 0000 tscon 0248 tse15 tse14 tse13 tse12 tse11 tse10 ts e9 tse8 tse7 tse6 tse5 tse4 tse3 tse2 tse1 tse0 0000 0000 0000 0000 rscon 024c rse15 rse14 rse13 rse12 rse11 rse10 rs e9 rse8 rse7 rse6 rse5 rse4 rse3 rse2 rse1 rse0 0000 0000 0000 0000 rxbuf0 0250 receive buffer #0 data register 0000 0000 0000 0000 rxbuf1 0252 receive buffer #1 data register 0000 0000 0000 0000 rxbuf2 0254 receive buffer #2 data register 0000 0000 0000 0000 rxbuf3 0256 receive buffer #3 data register 0000 0000 0000 0000 txbuf0 0258 transmit buffer #0 data register 0000 0000 0000 0000 txbuf1 025a transmit buffer #1 data register 0000 0000 0000 0000 txbuf2 025c transmit buffer #2 data register 0000 0000 0000 0000 txbuf3 025e transmit buffer #3 data register 0000 0000 0000 0000 legend: u = uninitialized bit
dspic30f ds70083g-page 144 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 145 dspic30f 19.0 12-bit analog-to-digital converter (a/d) module the 12-bit analog-to-digi tal converter (a/d) allows conversion of an analog input signal to a 12-bit digital number. this module is based on a successive approximation register (s ar) architecture and pro- vides a maximum sampling rate of 100 ksps. the a/d module has up to 16 analo g inputs which are multi- plexed into a sample and ho ld amplifier. the output of the sample and hold is the input into the converter which generates the result. the analog reference volt- age is software selectable to either the device supply voltage (av dd /av ss ) or the voltage level on the (v ref +/v ref -) pin. the a/d converter has a unique feature of being able to op erate while the device is in sleep mode with rc oscillator selection. the a/d module has six 16-bit registers: a/d control register 1 (adcon1) a/d control register 2 (adcon2) a/d control register 3 (adcon3) a/d input select register (adchs) a/d port configuration register (adpcfg) a/d input scan select ion register (adcssl) the adcon1, adcon2 and adcon3 registers con- trol the operation of the a/d module. the adchs reg- ister selects the input cha nnels to be converted. the adpcfg register configures the port pins as analog inputs or as digital i/o. the adcssl register selects inputs for scanning. the block diagram of the 12-bit a/d module is shown in figure 19-1. figure 19-1: 12-bit a/d functional block diagram note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). note: the ssrc<2:0>, asam, smpi<3:0>, bufm and alts bits, as well as the adcon3 and adcssl registers, must not be written to while adon = 1 . this would lead to indeterminate results. comparator 12-bit sar conversion logic v ref + av ss av dd dac data format 16-word, 12-bit dual port buffer bus interface an12 0000 0101 0111 1001 1101 1110 1111 1100 0001 0010 0011 0100 0110 1000 1010 1011 an13 an14 an15 an8 an9 an10 an11 an4 an5 an6 an7 an0 an1 an2 an3 ch0 ch0r ch0g v ref - sample/sequence control sample input mux control input switches s/h
dspic30f ds70083g-page 146 preliminary ? 2004 microchip technology inc. 19.1 a/d result buffer the module contains a 16-word dual port read only buffer, called adcbuf0...adcbuff, to buffer the a/d results. the ram is 12 bits wide but the data obtained is represented in one of four different 16-bit data for- mats. the contents of the sixteen a/d conversion result buffer registers, adcbuf0 through adcbuff, cannot be written by user software. 19.2 conversion operation after the a/d module has b een configured, the sample acquisition is started by se tting the samp bit. various sources, such as a programmable bit, timer time-outs and external events, will te rminate acquisition and start a conversion. when the a/d conversion is complete, the result is loaded into adcbuf0...adcbuff, and the done bit and the a/d interrupt flag adif are set after the number of samples specified by the smpi bit. the adc module can be configur ed for different interrupt rates as described in section 19.3. the following steps should be followed for doing an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o select a/d input channels select a/d conversion clock select a/d conversion trigger turn on a/d module 2. configure a/d interrupt (if required): clear adif bit select a/d interrupt priority 3. start sampling. 4. wait the required acquisition time. 5. trigger acquisition end, start conversion: 6. wait for a/d conversion to complete, by either: waiting for the a/d interrupt, or waiting for the done bit to get set. 7. read a/d result buffer, clear adif if required. 19.3 selecting the conversion sequence several groups of control bi ts select the sequence in which the a/d connects inpu ts to the sample/hold channel, converts a channel, writes the buffer memory and generates interrupts. the sequence is controlled by the sampling clocks. the smpi bits select the number of acquisition/ conversion sequences that would be performed before an interrupt occurs. this can vary from 1 sample per interrupt to 16 samples per interrupt. the bufm bit will split the 16-word results buffer into two 8-word groups. writing to the 8-word buffers will be alternated on each interrupt event. use of the bufm bit will depend on how much time is available for the moving of the buffers after the interrupt. if the processor can quickly unload a full buffer within the time it takes to acqu ire and convert one channel, the bufm bit can be ? 0 ? and up to 16 conversions (cor- responding to the 16 input channels) may be done per interrupt. the processor w ill have one acquisition and conversion time to move the sixteen conversions. if the processor cannot unload the buffer within the acquisition and conversion time, the bufm bit should be ? 1 ?. for example, if smpi<3:0> (adcon2<5:2>) = 0111 , then eight conversions will be loaded into 1/2 of the buffer, following which an interrupt occurs. the next eight conversions will be loaded into the other 1/2 of the buffer. the processor will have the entire time between interrupts to move the eight conversions. the alts bit can be used to alternate the inputs selected during the samp ling sequence. the input multiplexer has two sets of sample inputs: mux a and mux b. if the alts bit is ? 0 ?, only the mux a inputs are selected for sampling. if the alts bit is ? 1 ? and smpi<3:0> = 0000 on the first sample/convert sequence, the mux a inputs are selected and on the next acquire/convert sequence, the mux b inputs are selected. the cscna bit (adcon2<10> ) will allow the multi- plexer input to be alternately scanned across a selected number of analog inputs for the mux a group. the inputs are selected by the adcssl register. if a particular bit in the adcssl register is ? 1 ?, the corre- sponding input is select ed. the inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. if the number of inputs selected is greater than the number of sa mples taken per interrupt, the higher numbered inputs are unused.
? 2004 microchip technology inc. preliminary ds70083g-page 147 dspic30f 19.4 programming the start of conversion trigger the conversion trigger will terminate acquisition and start the requested conversions. the ssrc<2:0> bits select the source of the conver- sion trigger. the ssrc bits provide for up to 4 alternate sources of conversion trigger. when ssrc<2:0> = 000 , the conversion trigger is under software control. cl earing the samp bit will cause the conversion trigger. when ssrc<2:0> = 111 (auto-start mode), the con- version trigger is under a/ d clock control. the samc bits select the number of a/d clocks between the start of acquisition and the start of conversion. this provides the fastest conversion rate s on multiple channels. samc must always be at least 1 clock cycle. other trigger sources can come from timer modules or external interrupts. 19.5 aborting a conversion clearing the adon bit during a conversion will abort the current conversion and st op the sampling sequenc- ing until the next sampling tr igger. the adcbuf will not be updated with the partia lly completed a/d conversion sample. that is, the adcbuf will continue to contain the value of the last comp leted conversion (or the last value written to the adcbuf register). if the clearing of the adon bit coincides with an auto- start, the clearing has a higher priority and a new conversion will not start. after the a/d conversi on is aborted, a 2 t ad wait is required before the next sampling may be started by setting the samp bit. 19.6 selecting the a/d conversion clock the a/d conversion requires 15 t ad . the source of the a/d conversion clock is software selected, using a six-bit counter. there are 64 possible options for t ad . equation 19-1: a/d conversion clock the internal rc oscillator is selected by setting the adrc bit. for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 667 nsec (for v dd = 5v). refer to the electrical specifications section for minimum t ad under other operating conditions. example 19-1 shows a sample calculation for the adcs<5:0> bits, assuming a device operating speed of 30 mips. example 19-1: a/d conversion clock calculation t ad = t cy * (0.5*(adcs<5:0> + 1)) minimum t ad = 667 nsec adcs<5:0> = 2 ? 1 t ad t cy t cy = 33 nsec (30 mips) = 2 ? 1 667 nsec 33 nsec = 39.4 therefore, set adcs<5:0> = 40 actual t ad = (adcs<5:0> + 1) t cy 2 = (40 + 1) 33 nsec 2 = 677 nsec
dspic30f ds70083g-page 148 preliminary ? 2004 microchip technology inc. 19.7 a/d acquisition requirements the analog input model of the 12-bit a/d converter is shown in figure 19-2. the total sampling time for the a/d is a function of the internal amplifier settling time and the holding capacitor charge time. for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the voltage level on the analog input pin. the source impedance (r s ), the interconnect impedance (r ic ), and the internal sampling switch (r ss ) impedance combine to directly affect the time required to charge the capacitor c hold . the combined impedance of the analog sources must therefore be small enough to fully charge the holding capacitor within the chosen sample time. to minimize the effects of pin leakage currents on the accuracy of the a/d con- verter, the maximum re commended source imped- ance, r s , is 2.5 k ? . after the analog input channel is selected (changed), this sa mpling function must be completed prior to starting the conversion. the internal holding capacitor will be in a discharged state prior to each sample operation. figure 19-2: 12-bit a/d converter analog input model c pin va rs anx v t = 0.6v v t = 0.6v i leakage r ic 250 ? sampling switch r ss c hold = dac capacitance v ss v dd = 18 pf 500 na legend: c pin v t i leakage r ic r ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch resistance = sample/hold capaci tance (from dac) various junctions note: c pin value depends on device package and is not tested. effect of c pin negligible if rs 2.5 k ? . r ss 3 k ?
? 2004 microchip technology inc. preliminary ds70083g-page 149 dspic30f 19.8 module power-down modes the module has 2 internal power modes. when the adon bit is ? 1 ?, the module is in active mode; it is fully powered and functional. when adon is ? 0 ?, the module is in off mode. the dig- ital and analog portions of the circuit are disabled for maximum current savings. in order to return to the active mode from off mode, the user must wait for the a dc circuitry to stabilize. 19.9 a/d operation during cpu sleep and idle modes 19.9.1 a/d operation during cpu sleep mode when the device enters sleep mode, all clock sources to the module are shutdown and stay at logic ? 0 ?. if sleep occurs in the middl e of a conversion, the con- version is aborted. the converter will not continue with a partially completed conversion on exit from sleep mode. register contents are not affected by the device entering or leaving sleep mode. the a/d module can operate during sleep mode if the a/d clock source is set to rc (adrc = 1 ). when the rc clock source is selected, the a/d module waits one instruction cycle before star ting the conversion. this allows the sleep instruction to be executed which elim- inates all digital switchi ng noise from the conversion. when the conversion is complete, the conv bit will be cleared and the result loaded into the adcbuf register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/ d module will then be turned off, although the adon bit will remain set. 19.9.2 a/d operation during cpu idle mode the adsidl bit selects if the module will stop on idle or continue on idle. if adsidl = 0 , the module will con- tinue operation on assertion of idle mode. if adsidl = 1 , the module will stop on idle. 19.10 effects of a reset a device reset forces all r egisters to their reset state. this forces the a/d module to be turned off, and any conversion and sampling sequ ence is aborted. the val- ues that are in the adcbuf registers are not modified. the a/d result register will contain unknown data after a power-on reset. 19.11 output formats the a/d result is 12 bits wide. the data buffer ram is also 12 bits wide. the 12-bit data can be read in one of four different formats. the form<1:0> bits select the format. each of the output fo rmats translates to a 16-bit result on the data bus. write data will always be in right justified (integer) format. figure 19-3: a/d output data formats ram contents: d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 read to bus: signed fractional d11 d10d09d08d07d06d05d04d03d02d01d000000 fractional d11d10d09d08d07d06d05d04d03d02d01d000000 signed integer d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 integer 0 0 0 0 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
dspic30f ds70083g-page 150 preliminary ? 2004 microchip technology inc. 19.12 configuring analog port pins the use of the adpcfg and tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs mu st have their correspond- ing tris bit set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. the a/d operation is indep endent of the state of the ch0sa<3:0>/ch0sb<3:0> bits and the tris bits. when reading the port regist er, all pins configured as analog input channels will read as cleared. pins configured as digital inputs will not convert an ana- log input. analog levels on any pin that is defined as a digital input (including the anx pins) may cause the input buffer to consume current that exceeds the device specifications. 19.13 connection considerations the analog inputs have diodes to v dd and v ss as esd protection. this requires that the analog input be between v dd and v ss . if the input voltage exceeds this range by greater than 0.3v (either direction), one of the diodes becomes forward biased and it may damage the device if the input current specification is exceeded. an external rc filter is sometimes added for anti- aliasing of the input signal. the r component should be selected to ensure that the sampling time requirements are satisfied. any external components connected (via high impedance) to an analo g input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin.
? 2004 microchip technology inc. preliminary ds70083g-page 151 dspic30f table 19-1: a/d converter register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bi t 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state adcbuf0 0280 ? ? ? ? adc data buffer 0 0000 uuuu uuuu uuuu adcbuf1 0282 ? ? ? ? adc data buffer 1 0000 uuuu uuuu uuuu adcbuf2 0284 ? ? ? ? adc data buffer 2 0000 uuuu uuuu uuuu adcbuf3 0286 ? ? ? ? adc data buffer 3 0000 uuuu uuuu uuuu adcbuf4 0288 ? ? ? ? adc data buffer 4 0000 uuuu uuuu uuuu adcbuf5 028a ? ? ? ? adc data buffer 5 0000 uuuu uuuu uuuu adcbuf6 028c ? ? ? ? adc data buffer 6 0000 uuuu uuuu uuuu adcbuf7 028e ? ? ? ? adc data buffer 7 0000 uuuu uuuu uuuu adcbuf8 0290 ? ? ? ? adc data buffer 8 0000 uuuu uuuu uuuu adcbuf9 0292 ? ? ? ? adc data buffer 9 0000 uuuu uuuu uuuu adcbufa 0294 ? ? ? ? adc data buffer 10 0000 uuuu uuuu uuuu adcbufb 0296 ? ? ? ? adc data buffer 11 0000 uuuu uuuu uuuu adcbufc 0298 ? ? ? ? adc data buffer 12 0000 uuuu uuuu uuuu adcbufd 029a ? ? ? ? adc data buffer 13 0000 uuuu uuuu uuuu adcbufe 029c ? ? ? ? adc data buffer 14 0000 uuuu uuuu uuuu adcbuff 029e ? ? ? ? adc data buffer 15 0000 uuuu uuuu uuuu adcon1 02a0 adon ?adsidl ? ? ? form<1:0> ssrc<2:0> ? ? asam samp done 0000 0000 0000 0000 adcon2 02a2 vcfg<2:0> ? ? cscna ? ? bufs ? smpi<3:0> bufm alts 0000 0000 0000 0000 adcon3 02a4 ? ? ? samc<4:0> adrc ? adcs<5:0> 0000 0000 0000 0000 adchs 02a6 ? ? ? ch0nb ch0sb<3:0> ? ? ? ch0na ch0sa<3:0> 0000 0000 0000 0000 adpcfg 02a8 pcfg15 pcfg14 pcfg13 pcfg12 pcfg11 pcfg10 pcfg9 pcfg8 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 adcssl 02aa cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 cssl7 cssl6 cssl5 css l4 cssl3 cssl2 cssl1 cssl0 0000 0000 0000 0000 legend: u = uninitialized bit
dspic30f ds70083g-page 152 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 153 dspic30f 20.0 system integration there are several features intended to maximize sys- tem reliability, minimize co st through elimination of external components, provide power saving operating modes and offer code protection: oscillator selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - programmable brown-out reset (bor) watchdog timer (wdt) power saving modes (sleep and idle) code protection unit id locations in-circuit serial programming (icsp) dspic30f devices have a watchdog timer which is permanently enabled via the configuration bits or can be software controlled. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power -up. one is the oscillator start-up timer (ost), inte nded to keep the chip in reset until the crystal oscillat or is stable. the other is the power-up timer (pwrt) which provides a delay on power-up only, designed to keep the part in reset while the power supply stabilizes. wi th these two timers on- chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, wa tchdog timer wake-up, or through an interrupt. severa l oscillator options are also made available to allow the pa rt to fit a wide variety of applications. in the idle mode, the clock sources are still active but the cpu is shut-off. the rc oscillator option saves system cost while the lp crystal option saves power. 20.1 oscillator system overview the dspic30f oscillator system has the following modules and features: various external and inte rnal oscillator options as clock sources an on-chip pll to boos t internal operating frequency a clock switching mech anism between various clock sources programmable clock post scaler for system power savings a fail-safe clock monitor (fscm) that detects clock failure and takes fail-safe measures clock control register (osccon) configuration bits for ma in oscillator selection configuration bits determine the clock source upon power-on reset (por) and brown-out reset (bor). thereafter, the clock sour ce can be changed between permissible clock source s. the osccon register controls the clock switchi ng and reflects system clock related status bits. table 20-1 provides a su mmary of the dspic30f oscillator operating modes. a simplified diagram of the oscillator system is shown in figure 20-1. note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030).
dspic30f ds70083g-page 154 preliminary ? 2004 microchip technology inc. table 20-1: oscillator operating modes oscillator mode description xtl 200 khz-4 mhz crystal on osc1:osc2. xt 4 mhz-10 mhz crystal on osc1:osc2. xt w/ pll 4x 4 mhz-10 mhz crysta l on osc1:osc2, 4x pll enabled. xt w/ pll 8x 4 mhz-10 mhz crysta l on osc1:osc2, 8x pll enabled. xt w/ pll 16x 4 mhz-10 mhz crysta l on osc1:osc2, 16x pll enabled (1) . lp 32 khz crystal on sosco:sosci (2) . hs 10 mhz-25 mhz crystal. hs/2 w/ pll 4x 10 mhz-25 mhz crys tal, divide by 2, 4x pll enabled. hs/2 w/ pll 8x 10 mhz-25 mhz crys tal, divide by 2, 8x pll enabled. hs/2 w/ pll 16x 10 mhz-25 mhz crys tal, divide by 2, 16x pll enabled. hs/3 w/ pll 4x 10 mhz-25 mhz crys tal, divide by 3, 4x pll enabled. hs/3 w/ pll 8x 10 mhz-25 mhz crys tal, divide by 3, 8x pll enabled. hs/3 w/ pll 16x 10 mhz-25 mhz crys tal, divide by 3, 16x pll enabled. ec external clock input (0-40 mhz). ecio external clock input (0-40 mhz), osc2 pin is i/o. ec w/ pll 4x external clock input (0-40 mhz), osc2 pin is i/o, 4x pll enabled (1) . ec w/ pll 8x external clock input (0-40 mhz), osc2 pin is i/o, 8x pll enabled (1) . ec w/ pll 16x external clock input (0-40 mhz), osc2 pin is i/o, 16x pll enabled (1) . erc external rc oscillator, osc2 pin is f osc /4 output (3) . ercio external rc oscillator, osc2 pin is i/o (3) . frc 8 mhz internal rc oscillator. frc w/ pll 4x 8 mhz internal rc oscillator, 4x pll enabled. frc w/ pll 8x 8 mhz internal rc oscillator, 8x pll enabled. frc w/ pll 16x 7.5 mhz internal rc oscillator, 16x pll enabled. lprc 512 khz internal rc oscillator. note 1: dspic30f maximum operating frequ ency of 120 mhz must be met. 2: lp oscillator can be conveniently shared as system clock, as well as real-time clock for timer1. 3: requires external r and c. fr equency operation up to 4 mhz. 4: some devices support a subset of the above modes. refer to indivi dual device data sheets for details.
? 2004 microchip technology inc. preliminary ds70083g-page 155 dspic30f figure 20-1: oscillator system block diagram primary osc1 osc2 sosco sosci oscillator 32 khz lp clock and control block switching oscillator x4, x8, x16 pll primary oscillator stability detector stability detector secondary oscillator programmable clock divider oscillator start-up timer fail-safe clock monitor (fscm) internal fast rc oscillator (frc) internal low power rc oscillator (lprc) pwrsav instruction wake-up request oscillator configuration bits system clock oscillator trap to timer1 lprc secondary osc por done primary osc f pll post<1:0> 2 fcksm<1:0> 2 pll lock cosc<2:0> nosc<2:0> oswen cf
dspic30f ds70083g-page 156 preliminary ? 2004 microchip technology inc. 20.2 oscillator configurations 20.2.1 initial clock source selection while coming out of power- on reset or brown-out reset, the device selects its clock source based on: a) fos<2:0> configuration bits that select one of four oscillator groups, b) and fpr<4:0> configuration bits that select one of 13 oscillator choices within the primary group. the selection is as shown in table 20-2. table 20-2: configuration bit values for clock selection note: some devices may have different fos and fpr values from table 20-2, depend- ing on the oscilla tor modes supported. refer to individual de vice data sheets for details. oscillator mode oscillator source fos<2:0> fpr<4:0> osc2 function ecio w/ pll 4x pll 1 1 101101 i/o ecio w/ pll 8x pll 1 1 101110 i/o ecio w/ pll 16x pll 1 1 101111 i/o frc w/ pll 4x pll 1 1 100001 i/o frc w/ pll 8x pll 1 1 101010 i/o frc w/ pll 16x pll 1 1 100011 i/o xt w/ pll 4x pll 1 1 100101 osc2 xt w/ pll 8x pll 1 1 100110 osc2 xt w/ pll 16x pll 1 1 100111 osc2 hs2 w/ pll 4x pll 1 1 110001 osc2 hs2 w/ pll 8x pll 1 1 110010 osc2 hs2 w/ pll 16x pll 1 1 110011 osc2 hs3 w/ pll 4x pll 1 1 110101 osc2 hs3 w/ pll 8x pll 1 1 110110 osc2 hs3 w/ pll 16x pll 1 1 110111 osc2 ecio external 0 1 101100 i/o xt external 0 1 100100 osc2 hs external 0 1 100010 osc2 ec external 0 1 101011 clkout erc external 0 1 101001 clkout ercio external 0 1 101000 i/o xtl external 0 1 100000 osc2 lp secondary 0 0 0xxxxx (notes 1, 2) frc internal frc 0 0 1xxxxx (notes 1, 2) lprc internal lprc 0 1 0xxxxx (notes 1, 2) note 1: osc2 pin function is determined by (fpr<4:0>). 2: note that osc1 pin cannot be used as an i/o pin even if the secondar y oscillator or an internal clock source is selected at all times.
? 2004 microchip technology inc. preliminary ds70083g-page 157 dspic30f 20.2.2 oscillator start-up timer (ost) in order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an oscillator start-up timer is included. it is a simple 10-bit counter that counts 1024 t osc cycles before releasing the oscillator clock to the rest of the system. the time-out period is designated as t ost . the t ost time is involved every time the oscillator has to restart (i.e., on por, bor and wake-up from sleep). the oscillator start-up timer is applied to the lp oscillator, xt, xtl, and hs modes (upon wa ke-up from sleep, por and bor) for the primary oscillator. 20.2.3 lp oscillator control enabling the lp oscillato r is controlled with two elements: 1. the current oscillator group bits cosc<2:0>. 2. the lposcen bit (oscon register). the lp oscillator is on (even during sleep mode) if lposcen = 1. the lp oscilla tor is the device clock if: cosc<2:0> = 00 (lp selected as main oscillator) and lposcen = 1 keeping the lp oscillator on at all times allows for a fast switch to the 32 khz system clock for lower power oper- ation. returning to the faster main oscillator will still require a start-up time 20.2.4 phase locked loop (pll) the pll multiplies the clock which is generated by the primary oscillator. the pll is selectable to have either gains of x4, x8, and x16. input and output frequency ranges are summarized in table 20-3. table 20-3: pll frequency range the pll features a lock output which is asserted when the pll enters a phase lo cked state. should the loop fall out of lock (e.g., due to noise), the lock signal will be rescinded. the state of this signal is reflected in the read only lock bit in the osccon register. 20.2.5 fast rc oscillator (frc) the frc oscillator is a fast (8 mhz nominal) internal rc oscillator. this oscillator is intended to provide reasonable device operating speeds without the use of an external crystal, ceramic resonator, or rc network. the frc oscillator can be used with the pll to obtain higher clock frequencies. the dspic30f operates from the frc oscillator when- ever the current oscillator se lection control bits in the osccon register (osccon<14:12>) are set to ? 001 ?. the four bit field specified by tun<3:0> (oscon <15:14> and oscon<11:10>) allows the user to tune the internal fast rc oscillator (nominal 8.0 mhz). the user can tune the frc oscillator within a range of +10.5% (840 khz) and -12% (960 khz) in steps of 1.50% around the factory-calibrated setting, see table 20-4. if osccon<14:12> are set to ?111? and fpr<4:0> are set to ?00101?, ?00110? or ?00111?, then a pll multiplier of 4, 8 or 16 (respectively) is applied. table 20-4: frc tuning f in pll multiplier f out 4 mhz-10 mhz x4 16 mhz-40 mhz 4 mhz-10 mhz x8 32 mhz-80 mhz 4 mhz-7.5 mhz x16 64 mhz-160 mhz note: when a 16x pll is used, the frc fre- quency must not be tuned to a frequency greater than 7.5 mhz. tun<3:0> bits frc frequency 0111 + 10.5% 0110 + 9.0% 0101 + 7.5% 0100 + 6.0% 0011 + 4.5% 0010 + 3.0% 0001 + 1.5% 0000 center frequency (oscillator is running at calibrated frequency) 1111 - 1.5% 1110 - 3.0% 1101 - 4.5% 1100 - 6.0% 1011 - 7.5% 1010 - 9.0% 1001 - 10.5% 1000 - 12.0%
dspic30f ds70083g-page 158 preliminary ? 2004 microchip technology inc. 20.2.6 low power rc oscillator (lprc) the lprc oscillator is a component of the watchdog timer (wdt) and oscillates at a nominal frequency of 512 khz. the lprc oscillator is the clock source for the power-up timer (pwrt) circuit, wdt, and clock monitor circuits. it may also be used to provide a low frequency clock source opti on for applications where power consumption is critic al and timing accuracy is not required the lprc oscillator is alwa ys enabled at a power-on reset because it is the cl ock source for the pwrt. after the pwrt expires, the lprc oscillator will remain on if one of th e following is true: the fail-safe clock monitor is enabled the wdt is enabled the lprc oscillator is selected as the system clock via the cosc<2:0> control bits in the osccon register if one of the above condition s is not true, the lprc will shut-off after the pwrt expires. 20.2.7 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the device to continue to operate even in the event of an oscillator failure. the fscm function is enabled by appropriately programming the fcksm configuration bits (clock switch and monitor selecti on bits) in the fosc device configuration register. if th e fscm function is enabled, the lprc internal oscillator wi ll run at all times (except during sleep mode) and will not be subject to control by the swdten bit. in the event of an oscillator failure, the fs cm will gen- erate a clock failure trap ev ent and will switch the sys- tem clock over to the frc os cillator. the user will then have the option to either at tempt to restart the oscillator or execute a controlled sh utdown. the user may decide to treat the trap as a warm reset by simply loading the reset address into the oscillato r fail trap vector. in this event, the cf (clock fail) status bit (osccon<3>) is also set whenever a clock failure is recognized. in the event of a clock failure, the wdt is unaffected and continues to run on the lprc clock. if the oscillator has a very slow start-up time coming out of por, bor or sleep, it is possible that the pwrt timer will expire before th e oscillator has started. in such cases, the fscm will be activated and the fscm will initiate a clock failure trap, and the cosc<2:0> bits are loaded with frc oscillator selection. this will effec- tively shut-off the original oscillator that was trying to start. the user may detect this situation and restart the oscillator in the clock fail trap isr. upon a clock failure detecti on, the fscm module will initiate a clock switch to the frc oscillator as follows: 1. the cosc bits (osccon<14:12>) are loaded with the frc oscillator selection value. 2. cf bit is set (osccon<3>). 3. oswen control bit (osccon<0>) is cleared. for the purpose of clock sw itching, the clock sources are sectioned into four groups: 1. primary 2. secondary 3. internal frc 4. internal lprc the user can switch between these functional groups but cannot switch between opti ons within a group. if the primary group is selected, then the choice within the group is always deter mined by the fpr<4:0> configuration bits. the osccon register holds the control and status bits related to clock switching. cosc<1:0>: read only status bits always reflect the current oscillator group in effect. nosc<2:0>: control bits which are written to indicate the new oscilla tor group of choice. - on por and bor, cosc<2:0> and nosc<1:0> are both loaded with the configuration bit values fos<2:0>. lock: the lock status bit indicates a pll lock. cf: read only status bit indicating if a clock fail detect has occurred. oswen: control bit changes from a ? 0 ? to a ? 1 ? when a clock transition sequence is initiated. clearing the oswen control bit will abort a clock transition in progress (used for hang-up situations). if configuration bits fcksm<2:0> = 1x , then the clock switching and fail-safe cloc k monitoring functions are disabled. this is the defau lt configuration bit setting. note 1: osc2 pin function is determined by the primary oscillator mode selection (fpr<4:0>). 2: osc1 pin cannot be used as an i/o pin even if the secondary oscillator or an internal clock source is selected at all times.
? 2004 microchip technology inc. preliminary ds70083g-page 159 dspic30f if clock switching is disabled, then the fos<2:0> and fpr<4:0> bits directly cont rol the oscillator selection and the cosc<2:0> bits do not control the clock selec- tion. however, these bits wi ll reflect the clock source selection. 20.2.8 protection against accidental writes to osccon a write to the osccon register is intentionally made difficult because it controls clock switching and clock scaling. to write to the osccon lo w byte, the following code sequence must be executed without any other instructions in between: byte write is allowed for one instruction cycle . write the desired value or use bit manipulation instruction. to write to the osccon high byte, the following instructions must be executed without any other instructions in between: byte write is allowed for one instruction cycle . write the desired value or use bit manipulation instruction. 20.3 reset the dspic30f differentiates between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset (during normal operation) e) programmable brown-out reset (bor) f) reset instruction g) reset caused by trap lockup (trapr) h) reset caused by illegal opcode or by using an uninitialized w register as an address pointer (iopuwr) different registers are affected in different ways by var- ious reset conditions. most registers are not affected by a wdt wake-up since this is viewed as the resump- tion of normal operation. status bits from the rcon register are set or cleared di fferently in different reset situations, as indicated in table 20-5. these bits are used in software to determin e the nature of the reset. a block diagram of the on-c hip reset circuit is shown in figure 20-2. a mclr noise filter is provided in the mclr reset path. the filter detects and ignores small pulses. internally generated resets do not drive mclr pin low. figure 20-2: reset system block diagram note: the application should not attempt to switch to a clock of frequency lower than 100 khz when the fail-safe clock monitor is enabled. if such clock switching is performed, the devi ce may generate an oscillator fail trap and switch to the fast rc oscillator. byte write ?0x46? to osccon low byte write ?0x57? to osccon low byte write ? 0x78 ? to osccon high byte write ? 0x9a ? to osccon high s r q mclr v dd v dd rise detect por sysrst sleep or idle brown-out reset boren reset instruction wdt module digital glitch filter bor trap conflict illegal opcode/ uninitialized w register
dspic30f ds70083g-page 160 preliminary ? 2004 microchip technology inc. 20.3.1 por: power-on reset a power-on event will generate an internal por pulse when a v dd rise is detected. the reset pulse will occur at the por circuit threshold voltage (v por ) which is nominally 1.85v. the device supply voltage character- istics must meet specified starting voltage and rise rate requirements. the por pulse will reset a por timer and place the device in the reset state. the por also selects the device clock sour ce identified by the oscil- lator configuration fuses. the por circuit inserts a small delay, t por , which is nominally 10 s and ensures that th e device bias cir- cuits are stable. furthermore, a user selected power- up time-out (t pwrt ) is applied. the t pwrt parameter is based on device configuration bits and can be 0 ms (no delay), 4 ms, 16 ms, or 64 ms. the total delay is at device power-up, t por + t pwrt . when these delays have expired, sysrst will be negated on the next leading edge of the q1 clock and the pc will jump to the reset vector. the timing for the sysrst signal is shown in figure 20-3 through figure 20-5. figure 20-3: time-out sequence on power-up (mclr tied to v dd ) figure 20-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 t pwrt t ost v dd internal por pwrt time-out ost time-out internal reset mclr t pwrt t ost v dd internal por pwrt time-out ost time-out internal reset mclr
? 2004 microchip technology inc. preliminary ds70083g-page 161 dspic30f figure 20-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
dspic30f ds70083g-page 162 preliminary ? 2004 microchip technology inc. 20.3.1.1 por with long crystal start-up time (with fscm enabled) the oscillator start-up circui try is not linked to the por circuitry. some crystal circuits (especially low fre- quency crystals) will have a relatively long start-up time. therefore, one or more of the following conditions is possible after the por timer and the pwrt have expired: the oscillator circuit ha s not begun to oscillate. the oscillator start-up ti mer has not expired (if a crystal oscillator is used). the pll has not achieved a lock (if pll is used). if the fscm is enabled and one of the above conditions is true, then a clock failur e trap will occur. the device will automatically switch to the frc oscillator and the user can switch to the desi red crystal oscillator in the trap isr. 20.3.1.2 operating without fscm and pwrt if the fscm is disabled and the power-up timer (pwrt) is also disabled, then the device will exit rap- idly from reset on power-up. if the clock source is frc, lprc, extrc or ec, it will be active immediately. if the fscm is disabled an d the system clock has not started, the device will be in a frozen state at the reset vector until the system clock starts. from the user?s perspective, the device will a ppear to be in reset until a system clock is available. 20.3.2 bor: programmable brown-out reset the bor (brown-out reset) module is based on an internal voltage reference circuit. the main purpose of the bor module is to gener ate a device reset when a brown-out condition occurs. brown-out conditions are generally caused by glitches on the ac mains (i.e., missing portions of the ac cycle waveform due to bad power transmission lines, or voltage sags due to exces- sive current draw when a large inductive load is turned on). the bor module allows se lection of one of the following voltage trip points: 2.0v 2.7v 4.2v 4.5v a bor will generate a reset pulse which will reset the device. the bor will select the clock source based on the device configuration bi t values (fos<1:0> and fpr<3:0>). furthermore, if an oscillator mode is selected, the bor will activate the oscillator start-up timer (ost). the system clock is held until ost expires. if the pll is used, then the clock will be held until the lock bit (osccon<5>) is ? 1 ?. concurrently, the por time-out (t por ) and the pwrt time-out (t pwrt ) will be applied befor e the internal reset is released. if t pwrt = 0 and a crystal oscillator is being used, then a nominal delay of t fscm = 100 s is applied. the total delay in this case is (t por + t fscm ). the bor status bit (rcon<1>) will be set to indicate that a bor has occurred. the bor circuit, if enabled, will continue to operate wh ile in sleep or idle modes and will reset the device should v dd fall below the bor threshold voltage. figure 20-6: external power-on reset circuit (for slow v dd power-up) note: the bor voltage trip points indicated here are nominal values provided for design guidance only. refer to the electrical specifications in the specific device data sheet for bor voltage limit specifications. note: dedicated supervisory devices, such as the mcp1xx and mcp8xx, may also be used as an external power-on reset circuit. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r should be suitably chosen so as to make sure that the voltage drop across r does not violate the device?s electrical specifications. 3: r1 should be suitably c hosen so as to limit any current flowing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown due to electrostatic discharge (esd), or electrical overstress (eos). c r1 r d v dd dspic30f mclr
? 2004 microchip technology inc. preliminary ds70083g-page 163 dspic30f table 20-5 shows the reset conditions for the rcon register. since the control bits within the rcon register are r/w, the information in th e table implies that all the bits are negated prior to the action specified in the condition column. table 20-5: initialization condit ion for rcon register: case 1 condition program counter trapr iopuwr extr swr wdto idle sleep por bor power-on reset 0x000000 0 0 0 0 0 0 0 1 1 brown-out reset 0x000000 0 0 0 0 0 0 0 0 1 mclr reset during normal operation 0x000000 0 0 1 0 0 0 0 0 0 software reset during normal operation 0x000000 0 0 0 1 0 0 0 0 0 mclr reset during sleep 0x000000 0 0 1 0 0 0 1 0 0 mclr reset during idle 0x000000 0 0 1 0 0 1 0 0 0 wdt time-out reset 0x000000 0 0 0 0 1 0 0 0 0 wdt wake-up pc + 2 0 0 0 0 1 0 1 0 0 interrupt wake-up from sleep pc + 2 (1) 000000100 clock failure trap 0x000004 0 0 0 0 0 0 0 0 0 trap reset 0x000000 1 0 0 0 0 0 0 0 0 illegal operation trap 0x000000 0 1 0 0 0 0 0 0 0 legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? note 1: when the wake-up is due to an enabled interrupt, the pc is loaded with the corresponding interrupt vector.
dspic30f ds70083g-page 164 preliminary ? 2004 microchip technology inc. table 20-6 shows a second example of the bit conditions for the rcon regist er. in this case, it is not assumed the user has set/cleared specific bits prior to action specified in the condition column. table 20-6: initialization cond ition for rcon register: case 2 condition program counter trapr iopuwr extr swr wdto idle sleep por bor power-on reset 0x000000 0 0 0 0 0 0 0 1 1 brown-out reset 0x000000 u u u u u u u 0 1 mclr reset during normal operation 0x000000 u u 1 0 0 0 0 u u software reset during normal operation 0x000000 u u 0 1 0 0 0 u u mclr reset during sleep 0x000000 u u 1 u 0 0 1 u u mclr reset during idle 0x000000 u u 1 u 0 1 0 u u wdt time-out reset 0x000000 u u 0 0 1 0 0 u u wdt wake-up pc + 2 u u u u 1 u 1 u u interrupt wake-up from sleep pc + 2 (1) uuuuuu1uu clock failure trap 0x000004 u u u u u u u u u trap reset 0x000000 1 u u u u u u u u illegal operation reset 0x000000 u 1 u u u u u u u legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? note 1: when the wake-up is due to an e nabled interrupt, the pc is loaded with the corresponding interrupt vector.
? 2004 microchip technology inc. preliminary ds70083g-page 165 dspic30f 20.4 watchdog timer (wdt) 20.4.1 watchdog timer operation the primary function of th e watchdog timer (wdt) is to reset the processor in the event of a software mal- function. the wdt is a free -running timer which runs off an on-chip rc oscillator , requiring no external com- ponent. therefore, the wdt timer will continue to oper- ate even if the main processor clock (e.g., the crystal oscillator) fails. 20.4.2 enabling and disabling the wdt the watchdog timer can be ?enabled? or ?disabled? only through a configuratio n bit (fwdten) in the configuration register, fwdt. setting fwdten = 1 enables the watchdog timer. the enabling is done when programming the device. by default, after chip erase, fwdten bit = 1 . any device programmer capable of programming dspic30f devices allows programmi ng of this and other configuration bits. if enabled, the wdt will increment until it overflows or ?times out?. a wdt time-out will force a device reset (except during sleep). to pr event a wdt time-out, the user must clear the watchdog timer using a clrwdt instruction. if a wdt times out during sl eep, the device will wake- up. the wdto bit in the rco n register will be cleared to indicate a wake-up resulting from a wdt time-out. setting fwdten = 0 allows user software to enable/ disable the watchdog timer via the swdten (rcon<5>) control bit. 20.5 low voltage detect the low voltage detect (lvd ) module is used to detect when the v dd of the device drops below a threshold value, v lvd , which is determined by the lvdl<3:0> bits (rcon<11:8>) and is thus user programmable. the internal voltage referenc e circuitry requires a nom- inal amount of time to stabilize, and the bgst bit (rcon<13>) indicates when the voltage reference has stabilized. in some devices, the lvd threshold voltage may be applied externally on the lvdin pin. the lvd module is enabled by setting the lvden bit (rcon<12>). 20.6 power saving modes there are two power saving st ates that can be entered through the execution of a special instruction, pwrsav ; these are sleep and idle. the format of the pwrsav instruction is as follows: pwrsav , where ? parameter ? defines idle or sleep mode. 20.6.1 sleep mode in sleep mode, the clock to the cpu and peripherals is shutdown. if an on-chip oscilla tor is being used, it is shutdown. the fail-safe clock monito r is not functional during sleep since there is no cl ock to monitor. however, lprc clock remains active if wdt is operational during sleep. the brown-out protection circuit and the low voltage detect circuit, if enabled, wi ll remain functional during sleep. the processor wakes up from sleep if at least one of the following conditions has occurred: any interrupt that is individually enabled and meets the required priority level any reset (por, bor and mclr ) wdt time-out on waking up from sleep mode, the processor will restart the same clock that wa s active prior to entry into sleep mode. when clock switching is enabled, bits cosc<1:0> will determine th e oscillator source that will be used on wake-up. if clock switch is disabled, then there is only one system clock. if the clock source is an oscillator, the clock to the device will be held off unti l ost times out (indicating a stable oscillator). if pll is used, the system clock is held off until lock = 1 (indicating that the pll is stable). in either case, t por , t lock and t pwrt delays are applied. if ec, frc, lprc or extrc oscillators are used, then a delay of t por (~ 10 s) is applied. this is the smallest delay possible on wa ke-up from sleep. moreover, if lp oscillator was active during sleep and lp is the oscillator used on wake-up, then the start-up delay will be equal to t por . pwrt delay and ost timer delay are not applied. in order to have -the small- est possible start-up delay when waking up from sleep, one of these faster wake- up options should be selected before entering sleep. note: if a por or bor occurred, the selection of the oscillator is based on the fos<1:0> and fpr<3:0> configuration bits.
dspic30f ds70083g-page 166 preliminary ? 2004 microchip technology inc. any interrupt that is individually enabled (using the cor- responding ie bit) and meets t he prevailing priority level will be able to wake-up the processor. the processor will process the interrupt and branch to the isr. the sleep status bit in the rcon register is set upon wake-up. all resets will wake-up the processor from sleep mode. any reset, other than por, will set the sleep status bit. in a por, th e sleep bit is cleared. if the watchdog timer is enabled, then the processor will wake-up from sleep mo de upon wdt time-out. the sleep and wdto status bits are both set. 20.6.2 idle mode in idle mode, the clock to the cpu is shutdown while peripherals keep running. un like sleep mode, the clock source remains active. several peripherals have a control bit in each module that allows them to operate during idle. lprc fail-safe clock remain s active if clock failure detect is enabled. the processor wakes up from id le if at least one of the following conditions has occurred: any interrupt that is indi vidually enabled (ie bit is ? 1 ?) and meets the required priority level any reset (por, bor, mclr ) wdt time-out upon wake-up from idle mode, the clock is re-applied to the cpu and instruction execution begins immedi- ately, starting with the instruction following the pwrsav instruction. any interrupt that is indivi dually enabled (using ie bit) and meets the prevailing prio rity level will be able to wake-up the processor. the processor will process the interrupt and branch to the isr. the idle status bit in the rcon register is set upon wake-up. any reset other than por will set the idle status bit. on a por, the id le bit is cleared. if watchdog timer is enabled, then the processor will wake-up from idle mode up on wdt time-out. the idle and wdto status bits are both set. unlike wake-up from sleep, there are no time delays involved in wake-up from idle. 20.7 device configuration registers the configuration bits in each device configuration reg- ister specify some of t he device modes and are programmed by a device programmer, or by using the in-circuit serial prog ramming? (icsp?) feature of the device. each device configuration register is a 24-bit register, but only the lo wer 16 bits of each regis- ter are used to hold config uration data. there are four device configuration registers available to the user: 1. f osc ( 0xf80000 ): oscillator configuration register 2. fwdt ( 0xf80002 ): watchdog timer configuration register 3. fborpor ( 0xf80004 ): bor and por configuration register 4. fgs ( 0xf8000a ): general code segment configuration register the placement of the config uration bits is automatically handled when you select the device in your device pro- grammer. the desired state of the configuration bits may be specified in the so urce code (dependent on the language tool used), or th rough the programming inter- face. after the device has been programmed, the appli- cation software may read the configuration bit values through the table read instru ctions. for additional infor- mation, please refer to the programming specifications of the device. note: in spite of variou s delays applied (t por , t lock and t pwrt ), the crystal oscillator (and pll) may not be active at the end of the time-out (e.g., for low frequency crys- tals). in such cases, if fscm is enabled, then the device will de tect this as a clock failure and process the clo ck failure trap, the frc oscillator will be enabled and the user will have to re-enable the crystal oscillator. if fscm is not enabled, then the device will simply suspend execution of code until the clock is stable and will re main in sleep until the oscillator clock has started. note: if the code protection configuration fuse bits (fgs and fgs) have been programmed, an erase of the entire code-protected device is only possible at voltages v dd 4.5v.
? 2004 microchip technology inc. preliminary ds70083g-page 167 dspic30f 20.8 peripheral module disable (pmd) registers the peripheral module disable (pmd) registers pro- vide a method to disable a peripheral module by stop- ping all clock sources suppli ed to that module. when a peripheral is disabled via t he appropriate pmd control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral will also be d isabled so writes to those registers will have no effect and read values will be invalid. a peripheral module will only be enabled if both the associated bit in the the pm d register is cleared and the peripheral is supported by the specific dspic vari- ant. if the peripheral is present in the device, it is enabled in the pmd register by default. 20.9 in-circuit debugger when mplab icd2 is selected as a debugger, the in- circuit debugging functiona lity is enabled. this func- tion allows simple debugging functions when used with mplab ide. when the device has this feature enabled, some of the resources ar e not available for general use. these resources include the first 80 bytes of data ram and two i/o pins. one of four pairs of debug i/o pins may be selected by the user using configurat ion options in mplab ide. these pin pairs are named emud/emuc, emud1/ emuc1, emud2/emuc2 and mud3/emuc3. in each case, the selected emud pin is the emulation/ debug data line, and the emuc pin is the emulation/ debug clock line. these pins will interface to the mplab icd 2 module available from microchip. the selected pair of debug i/o pins is used by mplab icd 2 to send commands and receive responses, as well as to send and receive data. to use the in-circuit debugger function of th e device, the design must implement icsp connections to mclr , v dd , v ss , pgc, pgd, and the selected emudx/emucx pin pair. this gives rise to two possibilities: 1. if emud/emuc is selected as the debug i/o pin pair, then only a 5-pin interface is required, as the emud and emuc pin functions are multi- plexed with the pgd and pgc pin functions in all dspic30f devices. 2. if emud1/emuc1, emud2/emuc2 or emud3/ emuc3 is selected as the debug i/o pin pair, then a 7-pin interface is required, as the emudx/emucx pin functions (x = 1, 2 or 3) are not multiplexed with the pgd and pgc pin functions. note: if a pmd bit is set, the corresponding mod- ule is disabled after a delay of 1 instruction cycle. similarly, if a pm d bit is cleared, the corresponding module is enabled after a delay of 1 instruction cycle (assuming the module control registers are already configured to enable module operation). note 1: in the dspic30f6011 and dspic30f6013 devices, the dcimd bit is readable and writeable, and will be read as ? 1 ? when set. 2: in the dspic30f3014 device, the t4md, t5md, ic7md, ic8md, oc3md, oc4md dcimd and c1md bits are readable and writeable, and will be reas as ? 1 ? when set. 3: in the dspic30f2011, dspic30f3012 and dspic30f2012 devices, the u2md bit is readable and wr iteable, and will be read as ? 1 ? when set.
dspic30f ds70083g-page 168 preliminary ? 2004 microchip technology inc. table 20-7: system integration register map table 20-8: device configuration register map note: refer to dspic30f family reference manua l (ds70046) for descriptions of register bit fields. sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state rcon 0740 trapr iopuwr bgst lvden lvdl<3:0> extr swr swdten wdto sleep idle bor por (note 1) osccon 0742 ? cosc<2:0> ? nosc<2:0> post<1:0> lock ?cf ? lposcen oswen (note 2) osctun 0774 ? ? tun3 tun2 tun1 tun0 0000 0000 0000 0000 pmd1 0770 t5md t4md t3md t2md t1md ? ? dcimd i2cmd u2md u1md spi2md spi1md c2md c1md adcmd 0000 0000 0000 0000 pmd2 0772 ic8md ic7md ic6md ic5md ic4md ic3md ic2md ic1md oc8md oc7md oc6md oc5md oc4md oc3md oc2md oc1md 0000 0000 0000 0000 note 1: reset state depends on type of reset. 2: reset state depends on configuration bits. file name addr. bits 23-16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bi t 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fosc f80000 ? fcksm<1:0> ? ? ? fos<2:0> ? ? ? fpr<4:0> fwdt f80002 ? fwdten ? ? ? ? ? ? ? ? ? fwpsa<1:0> fwpsb<3:0> fborpor f80004 ? mclren ? ? ? ? ? ? ?boren ? borv<1:0> ? ? fpwrt<1:0> fgs f8000a ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? gcp gwrp
? 2004 microchip technology inc. preliminary ds70083g-page 169 dspic30f 21.0 instruction set summary the dspic30f instruction set adds many enhancements to the previous picmicro ? instruction sets, while maintaining an easy migration from picmicro instruction sets. most instructions are a single program memory word (24 bits). only three instructions require two program memory locations. each single word instruction is a 24-bit word divided into an 8-bit opcode which specifies the instruction type, and one or more oper ands which further specify the operation of the instruction. the instruction set is high ly orthogonal and is grouped into five basic categories: ? word or byte-oriented operations ? bit-oriented operations ? literal operations ? dsp operations ? control operations table 21-1 shows the general symbols used in describing the instructions. the dspic30f instruction set summary in table 21-2 lists all the instructions, al ong with the status flags affected by each instruction. most word or byte-orient ed w register instructions (including barrel shift instructions) have three operands: ? the first source operand which is typically a register wb without any address modifier ? the second source operan d which is typically a register ws with or wi thout an address modifier ? the destination of the result which is typically a register wd with or wi thout an address modifier however, word or byte-oriente d file register instructions have two operands: ? the file register specified by the value f ? the destination, which could either be the file register f or the w0 register, which is denoted as wreg most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: ? the w register (with or without an address modifier) or file register (specified by the value of ws or f) ? the bit in the w register or file register (specified by a literal value or indirectly by the contents of register wb) the literal instructions that involve data movement may use some of the following operands: ? a literal value to be loaded into a w register or file register (specified by the value of k) ? the w register or file register where the literal value is to be loaded (specified by wb or f) however, literal instructions that involve arithmetic or logical operations use some of the following operands: ? the first source operand which is a register wb without any address modifier ? the second source op erand which is a literal value ? the destination of the resu lt (only if not the same as the first source opera nd) which is typically a register wd with or wi thout an address modifier the mac class of dsp instructions may use some of the following operands: ? the accumulator (a or b) to be used (required operand) ? the w registers to be used as the two operands ? the x and y address space pre-fetch operations ? the x and y address space pre-fetch destinations ? the accumulator write back destination the other dsp instructions do not involve any multiplication, and may include: ? the accumulator to be used (required) ? the source or destination operand (designated as wso or wdo, respectively) with or without an address modifier ? the amount of shift specif ied by a w register wn or a literal value the control instructions may use some of the following operands: ? a program memory address ? the mode of the table read and table write instructions note: this data sheet summarizes features of this group of dspic30f devices and is not intended to be a complete reference source. for more information on the cpu, peripherals, register desc riptions and general device functionality, refer to the dspic30f family reference manual (ds70046). for more information on the device instruction set and programming, refer to the dspic30f programmer?s reference manual (ds70030).
dspic30f ds70083g-page 170 preliminary ? 2004 microchip technology inc. all instructions are a single word, except for certain double-word instructions, which were made double- word instructions so that all the required information is available in these 48 bits. in the second word, the 8 msbs are 0 s. if this second word is executed as an instruction (by itself), it will execute as a nop . most single word instructio ns are executed in a single instruction cycle, unless a condi tional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the ex ecution takes two instruction cycles with the addi tional instruction cycle(s) executed as a nop . notable exceptions are the bra (uncondi- tional/computed branch), indirect call/goto , all table reads and writes, and return/retfie instructions, which are single word instructions but take two or three cycles. certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is perfo rmed, depending on whether the instruction being skipped is a single word or two- word instruction. more over, double-word moves require two cycles. the double-word instructions execute in two instruction cycles. note: for more details on the instruction set, refer to the programmers reference manual. table 21-1: symbols used in opcode descriptions field description #text means literal defined by ? text ? (text) means ?content of text ? [text] means ?the location addressed by text ? { } optional field or operation register bit field .b byte mode selection .d double-word mode selection .s shadow register select .w word mode selection (default) acc one of two accumulators {a, b} awb accumulator write back dest ination address register {w13, [w13]+=2} bit4 4-bit bit selection field (used in word addressed instructions) {0...15} c, dc, n, ov, z mcu status bits: carry, digit carry, negative, overflow, sticky zero expr absolute address, label or expression (resolved by the linker) f file register address {0x0000...0x1fff} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for byte mode, {0:1023} for word mode lit14 14-bit unsigned literal {0...16384} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388608}; lsb must be 0 none field does not require an entry, may be blank oa, ob, sa, sb dsp status bits: acca overflow, accb overflow, acca saturate, accb saturate pc program counter slit10 10-bit signed literal {-512...511} slit16 16-bit signed literal {-32768...32767} slit6 6-bit signed literal {-16...16}
? 2004 microchip technology inc. preliminary ds70083g-page 171 dspic30f wb base w register {w0..w15} wd destination w register { wd, [wd], [wd++], [wd--], [++wd], [--wd] } wdo destination w register { wnd, [wnd], [wnd++], [wnd--], [++wnd], [--wnd], [wnd+wb] } wm,wn dividend, divisor working register pair (direct addressing) wm*wm multiplicand and multip lier working register pair for square instructions {w4*w4,w5*w5,w6*w6,w7*w7} wm*wn multiplicand and mult iplier working register pa ir for dsp instructions {w4*w5,w4*w6,w4*w7,w5*w6,w5*w7,w6*w7} wn one of 16 working registers {w0..w15} wnd one of 16 destination working registers {w0..w15} wns one of 16 source working registers {w0..w15} wreg w0 (working register used in file register instructions) ws source w register { ws, [ws], [ws++], [ws--], [++ws], [--ws] } wso source w register { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] } wx x data space pre-fetch address register for dsp instructions {[w8]+=6, [w8]+=4, [w8] +=2, [w8], [w8]-=6, [w8]-=4, [w8]-=2, [w9]+=6, [w9]+=4, [w9]+=2, [w9], [w9]-=6, [w9]-=4, [w9]-=2, [w9+w12],none} wxd x data space pre-fetch destinati on register for dsp instructions {w4..w7} wy y data space pre-fetch address register for dsp instructions {[w10]+=6, [w10]+=4, [w10]+=2, [w 10], [w10]-=6, [w10]-=4, [w10]-=2, [w11]+=6, [w11]+=4, [w11]+=2, [w11], [w11]-=6, [w11]-=4, [w11]-=2, [w11+w12], none} wyd y data space pre-fetch destinati on register for dsp instructions {w4..w7} table 21-1: symbols used in opcode descriptions (continued) field description
dspic30f ds70083g-page 172 preliminary ? 2004 microchip technology inc. table 21-2: instruction set overview base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected 1 add add acc add accumulators 1 1 oa,ob,sa,sb add f f = f + wreg 1 1 c,dc,n,ov,z add f,wreg wreg = f + wreg 1 1 c,dc,n,ov,z add #lit10,wn wd = lit10 + wd 1 1 c,dc,n,ov,z add wb,ws,wd wd = wb + ws 1 1 c,dc,n,ov,z add wb,#lit5,wd wd = wb + lit5 1 1 c,dc,n,ov,z add wso,#slit4,acc 16-bit signed add to accumulator 1 1 oa,ob,sa,sb 2 addc addc f f = f + wreg + (c) 1 1 c,dc,n,ov,z addc f,wreg wreg = f + wreg + (c) 1 1 c,dc,n,ov,z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c,dc,n,ov,z addc wb,ws,wd wd = wb + ws + (c) 1 1 c,dc,n,ov,z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c,dc,n,ov,z 3 and and f f = f .and. wreg 1 1 n,z and f,wreg wreg = f .and. wreg 1 1 n,z and #lit10,wn wd = lit10 .and. wd 1 1 n,z and wb,ws,wd wd = wb .and. ws 1 1 n,z and wb,#lit5,wd wd = wb .and. lit5 1 1 n,z 4 asr asr f f = arithmetic right shift f 1 1 c,n,ov,z asr f,wreg wreg = arithmetic right shift f 1 1 c,n,ov,z asr ws,wd wd = arithmetic right shift ws 1 1 c,n,ov,z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n,z asr wb,#lit5,wnd wnd = arithmetic right s hift wb by lit5 1 1 n,z 5 bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none 6 bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nov,expr branch if not overflow 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra oa,expr branch if accumulator a overflow 1 1 (2) none bra ob,expr branch if accumulator b overflow 1 1 (2) none bra ov,expr branch if overflow 1 1 (2) none bra sa,expr branch if accumulator a saturated 1 1 (2) none bra sb,expr branch if accumulator b saturated 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none 7 bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none 8 bsw bsw.c ws,wb write c bit to ws 1 1 none bsw.z ws,wb write z bit to ws 1 1 none
? 2004 microchip technology inc. preliminary ds70083g-page 173 dspic30f 9 btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none 10 btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none 11 btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none 12 btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws to c 1 1 c btst.z ws,wb bit test ws to z 1 1 z 13 btsts btsts f,#bit4 bit test then set f 1 1 z btsts.c ws,#bit4 bit test ws to c, then set 1 1 c btsts.z ws,#bit4 bit test ws to z, then set 1 1 z 14 call call lit23 call subroutine 2 2 none call wn call indirect subroutine 1 2 none 15 clr clr f f = 0x0000 1 1 none clr wreg wreg = 0x0000 1 1 none clr ws ws = 0x0000 1 1 none clr acc,wx,wxd,wy,wyd,awb clear accumulator 1 1 oa,ob,sa,sb 16 clrwdt clrwdt clear watchdog timer 1 1 wdto,sleep 17 com com f f = f 11 n,z com f,wreg wreg = f 11 n,z com ws,wd wd = ws 11 n,z 18 cp cp f compare f with wreg 1 1 c,dc,n,ov,z cp wb,#lit5 compare wb with lit5 1 1 c,dc,n,ov,z cp wb,ws compare wb with ws (wb - ws) 1 1 c,dc,n,ov,z 19 cp0 cp0 f compare f with 0x0000 1 1 c,dc,n,ov,z cp0 ws compare ws with 0x0000 1 1 c,dc,n,ov,z 20 cp1 cp1 f compare f with 0xffff 1 1 c,dc,n,ov,z cp1 ws compare ws with 0xffff 1 1 c,dc,n,ov,z 21 cpb cpb f compare f with wreg , with borrow 1 1 c,dc,n,ov,z cpb wb,#lit5 compare wb with lit5, with borrow 1 1 c,dc,n,ov,z cpb wb,ws compare wb with ws, with borrow (wb - ws - c ) 1 1 c,dc,n,ov,z 22 cpseq cpseq wb, wn compare wb with wn, skip if = 1 1 (2 or 3) none 23 cpsgt cpsgt wb, wn compare wb with wn, skip if > 1 1 (2 or 3) none 24 cpslt cpslt wb, wn compare wb with wn, skip if < 1 1 (2 or 3) none 25 cpsne cpsne wb, wn compare wb with wn, skip if 11 (2 or 3) none 26 daw daw wn wn = decimal adjust wn 1 1 c 27 dec dec f f = f -1 1 1 c,dc,n,ov,z dec f,wreg wreg = f -1 1 1 c,dc,n,ov,z dec ws,wd wd = ws - 1 1 1 c,dc,n,ov,z 28 dec2 dec2 f f = f -2 1 1 c,dc,n,ov,z dec2 f,wreg wreg = f -2 1 1 c,dc,n,ov,z dec2 ws,wd wd = ws - 2 1 1 c,dc,n,ov,z table 21-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
dspic30f ds70083g-page 174 preliminary ? 2004 microchip technology inc. 29 disi disi #lit14 disable interrupts for k instruction cycles 1 1 none 30 div div.s wm,wn signed 16/16-bit integer divide 1 18 n,z,c,ov div.sd wm,wn signed 32/16-bit in teger divide 1 18 n,z,c,ov div.u wm,wn unsigned 16/16-bit in teger divide 1 18 n,z,c,ov div.ud wm,wn unsigned 32/16-bit in teger divide 1 18 n,z,c,ov 31 divf divf wm, wn signed 16/16-bit fractional divide 1 18 n,z,c,ov 32 do do #lit14,expr do code to pc+expr, lit14+1 times 2 2 none do wn,expr do code to pc+expr, (wn)+1 times 2 2 none 33 ed ed wm*wm,acc,wx,wy,wxd euclidean dis tance (no accumulate) 1 1 oa,ob,oab, sa,sb,sab 34 edac edac wm*wm,acc,wx,wy,wx d euclidean distance 1 1 oa,ob,oab, sa,sb,sab 35 exch exch wns,wnd swap wns with wnd 1 1 none 36 fbcl fbcl ws,wnd find bit chan ge from left (msb) side 1 1 c 37 ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c 38 ff1r ff1r ws,wnd find first one f rom right (lsb) side 1 1 c 39 goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none 40 inc inc f f = f + 1 1 1 c,dc,n,ov,z inc f,wreg wreg = f + 1 1 1 c,dc,n,ov,z inc ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 41 inc2 inc2 f f = f + 2 1 1 c,dc,n,ov,z inc2 f,wreg wreg = f + 2 1 1 c,dc,n,ov,z inc2 ws,wd wd = ws + 2 1 1 c,dc,n,ov,z 42 ior ior f f = f .ior. wreg 1 1 n,z ior f,wreg wreg = f .ior. wreg 1 1 n,z ior #lit10,wn wd = lit10 .ior. wd 1 1 n,z ior wb,ws,wd wd = wb .ior. ws 1 1 n,z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n,z 43 lac lac wso,#slit4,acc l oad accumulator 1 1 oa,ob,oab, sa,sb,sab 44 lnk lnk #lit14 link frame pointer 1 1 none 45 lsr lsr f f = logical right shift f 1 1 c,n,ov,z lsr f,wreg wreg = logical right shift f 1 1 c,n,ov,z lsr ws,wd wd = logical right shift ws 1 1 c,n,ov,z lsr wb,wns,wnd wnd = logical ri ght shift wb by wns 1 1 n,z lsr wb,#lit5,wnd wnd = logical ri ght shift wb by lit5 1 1 n,z 46 mac mac wm*wn,acc,wx,wxd,wy,wyd, awb multiply and accumulate 1 1 oa,ob,oab, sa,sb,sab mac wm*wm,acc,wx,wxd,wy,wyd square and accumulate 1 1 oa,ob,oab, sa,sb,sab 47 mov mov f,wn move f to wn 1 1 none mov f move f to f 1 1 n,z mov f,wreg move f to wreg 1 1 n,z mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 n,z mov.d wns,wd move d ouble from w(ns):w(ns+1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd+1):w(nd) 1 2 none 48 movsac movsac acc,wx,wxd,wy,wyd,aw b pre-fetch and store accumulator 1 1 none table 21-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2004 microchip technology inc. preliminary ds70083g-page 175 dspic30f 49 mpy mpy wm*wn, acc,wx,wxd,wy,wyd multiply wm by wn to accumulator 1 1 oa,ob,oab, sa,sb,sab mpy wm*wm, acc,wx,wxd,wy,wyd square wm to accumulator 1 1 oa,ob,oab, sa,sb,sab 50 mpy.n mpy.n wm*wn,acc,wx,wxd,w y,wyd -(multiply wm by wn) to accumulator 1 1 none 51 msc msc wm*wm,acc,wx,wxd,wy,wyd, awb multiply and subtract from accumulator 1 1 oa,ob,oab, sa,sb,sab 52 mul mul.ss wb,ws,wnd {wnd+1, wnd } = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd+1, wnd} = signed(wb) * unsigned(ws) 1 1 none mul.us wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * signed(ws) 1 1 none mul.uu wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(ws) 1 1 none mul.su wb,#lit5,wnd {wnd+1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(lit5) 1 1 none mul f w3:w2 = f * wreg 1 1 none 53 neg neg acc negate accumulator 1 1 oa,ob,oab, sa,sb,sab neg f f = f + 1 1 1 c,dc,n,ov,z neg f,wreg wreg = f + 1 1 1 c,dc,n,ov,z neg ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 54 nop nop no operation 1 1 none nopr no operation 1 1 none 55 pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-sta ck (tos) to wdo 1 1 none pop.d wnd pop from top-of -stack (tos) to w(nd):w(nd+1) 1 2 none pop.s pop shadow registers 1 1 all 56 push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns+1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none 57 pwrsav pwrsav #lit 1 go into sleep or idle mode 1 1 wdto,sleep 58 rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none 59 repeat repeat #lit14 repeat ne xt instruction lit14+1 times 1 1 none repeat wn repeat next instruction (wn)+1 times 1 1 none 60 reset reset software device reset 1 1 none 61 retfie retfie return from interrupt 1 3 (2) none 62 retlw retlw #lit10,wn return with literal in wn 1 3 (2) none 63 return return return from subroutine 1 3 (2) none 64 rlc rlc f f = rotate left through carry f 1 1 c,n,z rlc f,wreg wreg = rotate left through carry f 1 1 c,n,z rlc ws,wd wd = rotate left through carry ws 1 1 c,n,z 65 rlnc rlnc f f = rotate left (no carry) f 1 1 n,z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n,z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n,z 66 rrc rrc f f = rotate right through carry f 1 1 c,n,z rrc f,wreg wreg = rotate right through carry f 1 1 c,n,z rrc ws,wd wd = rotate right through carry ws 1 1 c,n,z 67 rrnc rrnc f f = rotate right (no carry) f 1 1 n,z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n,z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n,z table 21-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
dspic30f ds70083g-page 176 preliminary ? 2004 microchip technology inc. 68 sac sac acc,#slit4,wdo store accumulator 1 1 none sac.r acc,#slit4,wdo store rounded accumulator 1 1 none 69 se se ws,wnd wnd = sign-extended ws 1 1 c,n,z 70 setm setm f f = 0xffff 1 1 none setm wreg wreg = 0xffff 1 1 none setm ws ws = 0xffff 1 1 none 71 sftac sftac acc,wn arithmetic s hift accumulator by (wn) 1 1 oa,ob,oab, sa,sb,sab sftac acc,#slit6 arithmetic shift accumulator by slit6 1 1 oa,ob,oab, sa,sb,sab 72 sl sl f f = left shift f 1 1 c,n,ov,z sl f,wreg wreg = left shift f 1 1 c,n,ov,z sl ws,wd wd = left shift ws 1 1 c,n,ov,z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n,z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n,z 73 sub sub acc subtract accumulators 1 1 oa,ob,oab, sa,sb,sab sub f f = f - wreg 1 1 c,dc,n,ov,z sub f,wreg wreg = f - wreg 1 1 c,dc,n,ov,z sub #lit10,wn wn = wn - lit10 1 1 c,dc,n,ov,z sub wb,ws,wd wd = wb - ws 1 1 c,dc,n,ov,z sub wb,#lit5,wd wd = wb - lit5 1 1 c,dc,n,ov,z 74 subb subb f f = f - wreg - (c ) 1 1 c,dc,n,ov,z subb f,wreg wreg = f - wreg - (c ) 1 1 c,dc,n,ov,z subb #lit10,wn wn = wn - lit10 - (c ) 1 1 c,dc,n,ov,z subb wb,ws,wd wd = wb - ws - (c ) 1 1 c,dc,n,ov,z subb wb,#lit5,wd wd = wb - lit5 - (c ) 1 1 c,dc,n,ov,z 75 subr subr f f = wreg - f 1 1 c,dc,n,ov,z subr f,wreg wreg = wreg - f 1 1 c,dc,n,ov,z subr wb,ws,wd wd = ws - wb 1 1 c,dc,n,ov,z subr wb,#lit5,wd wd = lit5 - wb 1 1 c,dc,n,ov,z 76 subbr subbr f f = wreg - f - (c ) 1 1 c,dc,n,ov,z subbr f,wreg wreg = wreg -f - (c ) 1 1 c,dc,n,ov,z subbr wb,ws,wd wd = ws - wb - (c ) 1 1 c,dc,n,ov,z subbr wb,#lit5,wd wd = lit5 - wb - (c ) 1 1 c,dc,n,ov,z 77 swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none 78 tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none 79 tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none 80 tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none 81 tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none 82 ulnk ulnk unlink frame pointer 1 1 none 83 xor xor f f = f .xor. wreg 1 1 n,z xor f,wreg wreg = f .xor. wreg 1 1 n,z xor #lit10,wn wd = lit10 .xor. wd 1 1 n,z xor wb,ws,wd wd = wb .xor. ws 1 1 n,z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n,z 84 ze ze ws,wnd wnd = zero-extend ws 1 1 c,z,n table 21-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2004 microchip technology inc. preliminary ds70083g-page 177 dspic30f 22.0 development support the picmicro ? microcontrollers are supported with a full range of hardware an d software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm? assembler - mplab c17 and mplab c18 c compilers - mplink? object linker/ mplib? object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator - mplab dspic30 software simulator ? emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer ? low cost demonstration boards - picdem? 1 demonstration board - picdem.net? demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board ? evaluation kits -k ee l oq ? - picdem msc - microid ? -can - powersmart ? -analog 22.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: ? an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high level source code debugging ? mouse over variable inspection ? extensive on-line help the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - absolute listing file (mixed assembly and c) - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to too ls with increasing flexibility and power. 22.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files th at contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process
dspic30f ds70083g-page 178 preliminary ? 2004 microchip technology inc. 22.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchips pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debug ging, the compilers provide symbol information that is optimized to the mplab ide debugger. 22.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from pre- compiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library file s of pre-compiled code. when a routine from a library is call ed from a source file, only the modules that contain that routine will be linked in with the application. this al lows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code mainta inability by grouping related modules together ? flexible creation of libra ries with easy module listing, replacement, de letion and extraction 22.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler a lso supports many command- line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties, and afford fine cont rol of the compiler code generator. mplab c30 is distributed wi th a complete ansi c standard library. all library functions have been vali- dated and conform to the an si c library standard. the library includes functions for string manipulation, dynamic memory allocation , data conversion, time- keeping, and math functi ons (trigonometric, exponen- tial and hyperbolic). the co mpiler provides symbolic information for high level source debugging with the mplab ide. 22.6 mplab asm30 assembler, linker, and librarian mplab asm30 assembler produces relocatable machine code from sym bolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire d spic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 22.7 mplab sim software simulator the mplab sim software simu lator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and st imuli can be applied from a file, or user defined key pr ess, to any pin. the execu- tion can be performed in single-step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers t he flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 22.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcon trollers on an instruction level. on any given instruction, the data areas can be examined or modified and st imuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for au tomated tasks, or from mplab ide. this high speed simulator is designed to debug, analyze and optim ize time intensive dsp routines.
? 2004 microchip technology inc. preliminary ds70083g-page 179 dspic30f 22.9 mplab ice 2000 high performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the pr oduct development engineer with a complete microcont roller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, build ing, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, tr igger and data monitoring features. interchangeable pr ocessor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circu it emulator system has been designed as a real-t ime emulation system with advanced features that ar e typically found on more expensive development tool s. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 22.10 mplab ice 4000 high performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the pr oduct development engineer with a complete microcontrol ler design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulat or is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory, and the ability to view variables in real-time. the mplab ice 4000 in-circu it emulator system has been designed as a real-t ime emulation system with advanced features that ar e typically found on more expensive development tool s. the pc platform and microsoft windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application. 22.11 mplab icd 2 in-circuit debugger microchips in-circuit debugger, mplab icd 2, is a powerful, low cost, run-time development tool, connecting to the host pc vi a an rs-232 or high speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchips in-circuit serial programming? (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user in terface of the mplab inte- grated development envi ronment. this enables a designer to develop and debu g source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral re gisters. running at full speed enables testing har dware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 22.12 pro mate ii universal device programmer the pro mate ii is a univers al, ce compliant device programmer with programmabl e voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instruct ions and error messages and a modular detachable so cket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, and program picmicro devices wi thout a pc connection. it can also set code protection in this mode. 22.13 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low cost, prot otype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant.
dspic30f ds70083g-page 180 preliminary ? 2004 microchip technology inc. 22.14 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic1 7c43 and pic17c44. all necessary hardware and so ftware is included to run basic demo programs. th e sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer, or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a pro- totype area extends the circu itry for additional applica- tion components. featur es include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 22.15 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip de vice that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit featur es a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interfac e, rs-232 interface, and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 22.16 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18-, 28-, and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. th e sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds, and sample pic18f452 and pic16f877 flash microcontrollers. 22.17 picdem 3 pic16c92x demonstration board the picdem 3 demonstrat ion board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 22.18 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8-, 14-, and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 fam- ily of microcontrollers. picdem 4 is intended to show- case the many features of these low pin count parts, including lin and motor control using eccp. special provisions are ma de for low power operation with the super capacitor circuit, and jumpers allow on-board hardware to be disabled to eliminate current draw in this mode. included on the demo board are provisions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, i cd connector for program- ming via icsp and develo pment with mplab icd 2, 2x16 liquid crystal display, pcb footprints for h-bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a prototyping area. included with the ki t is a pic16f627a and a pic18f1320. tutorial firmwa re is included along with the users guide. 22.19 picdem 17 demonstration board the picdem 17 demonstratio n board is an evaluation board that demonstrates the capabilities of several microchip microcontrolle rs, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is includ ed. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to re program the device for user tailored application de velopment. the picdem 17 demonstration board suppor ts program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion.
? 2004 microchip technology inc. preliminary ds70083g-page 181 dspic30f 22.20 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstrat ion board serves to assist development of the pic18c601/ 801 family of microchip microcontrollers. it provid es hardware implementation of both 8-bit multiplexed/de-multiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 22.21 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash micro- controller serves as the ma ster. all three microcontrol- lers are programmed with firmware to provide lin bus communication. 22.22 pickit ? 1 flash starter kit a complete "development system in a box", the pickit flash starter kit includes a convenient multi-section board for programming, eval uation, and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates un der a simple windows gui. the pickit 1 starter kit in cludes the user's guide (on cd rom), pickit 1 tutorial software and code for vari- ous applications. also included are mplab ? ide (inte- grated development environment) software, software and hardware "tips 'n tricks for 8-pin flash pic ? microcontrollers" handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 22.23 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this boar d provides the basis for future usb products. 22.24 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kit s and demonstration software for these products. ?k ee l oq evaluation and prog ramming tools for microchips hcs secure data products ? can developers kit fo r automotive network applications ? analog design boards and filter design software ? powersmart battery charging evaluation/ calibration kits ?irda ? development kit ? microid development and rflab? development software ? seeval ? designer kit for memory evaluation and endurance calculations ? picdem msc demo boards for switching mode power supply, high power ir driver, delta sigma adc, and flow rate sensor check the microchip web pa ge and the latest product line card for the complete list of demonstration and evaluation kits.
dspic30f ds70083g-page 182 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 183 dspic30f 23.0 electrical characteristics this section provides an overview of ds pic30f electrical characteristics. additio nal information will be provided in future revisions of this document as it becomes available. for detailed information about the dspic3 0f architecture and core, refer to dspic30f family reference manual (ds70046). absolute maximum ratings for the dspic 30f family are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional opera tion of the device at these or any other conditions above the parameters indicated in t he operation listings of this specification is not implied. absolute maximum ratings (?) ambient temperature under bias...... .............................................. ............................................. ............-40c to +125c storage temperature .............................. ........................................ ...................................... .................. -65c to +150c voltage on any pin with respect to v ss (except v dd and mclr ) .......................................... ......... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ........................................ ........................................ ......................... -0.3v to +5.5v voltage on mclr with respect to v ss (note 1) .............................................. ........................................... 0v to +13.25v total power dissipation (note 2) ........................................ .............................................. ......................................... 1.0w maximum current out of v ss pin ................................... ............................................. ........................................... 300 ma maximum current into v dd pin ................................ .............................................. ............................................. ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ........................................ .............................................. ....................20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ....................................... ........................................ .................... 20 ma maximum output current sunk by any i/o pin..................... ................................... ............................. .....................25 ma maximum output current sourced by any i/o pin ................................ ............................. ..................... ..................25 ma maximum current sunk by all ports .. .................................. ................................... ....................... .........................200 ma maximum current sourced by all port s ........................................... ............................ .................... .......................200 ma note 1: power dissipation is ca lculated as follows: pdis = v dd x {i dd - i oh } + {(v dd - v oh ) x i oh } + (v o l x i ol ) 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latchup. thus, a series re sistor of 50-100 ? should be used when applyi ng a low level to the mclr /v pp pin, rather than pulling this pin directly to v ss . note: the specifications listed in this sect ion are provided for desi gn guidance only. please refer to the individual device data sheets for electrical char acteristics specific to each device. ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating onl y and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. ex posure to maximum rating conditions for extended periods may affe ct device reliability. note: all peripheral electrical characteristics are specif ied. for exact peripherals available on specific devices, please refer the the family cross reference table.
dspic30f ds70083g-page 184 preliminary ? 2004 microchip technology inc. 23.1 dc characteristics table 23-1: operating mips vs. voltage v dd range temp range max mips dspic30fxxx-30i dspic30fxxx-20i dspic30fxxx-20e 4.5-5.5v -40c to 85c 30 20 4.5-5.5v -40c to 125c 20 3.0-3.6v -40c to 85c 15 10 3.0-3.6v -40c to 125c 10 2.5-3.0v -40c to 85c 10 7.5 table 23-2: dc temperature and voltage specifications dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions operating voltage (2) dc10 v dd supply voltage 2.5 5.5 v industrial temperature dc11 v dd supply voltage 3.0 5.5 v extended temperature dc12 v dr ram data retention voltage (3) 1.5v dc16 v por v dd start voltage to ensure internal power-on reset signal v ss v dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 v/ms 0-5v in 0.1 sec 0-3v in 60 ms note 1: data in typ column is at 5v, 25 c unless otherwise stated. paramete rs are for design guidance only and are not tested. 2: these parameters are characterize d but not tested in manufacturing. 3: this is the limit to which v dd can be lowered with out losing ram data.
? 2004 microchip technology inc. preliminary ds70083g-page 185 dspic30f table 23-3: dc characteristics: operating current (i dd ) dc characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions operating current (i dd ) (2) dc20 ma -40c 3.3v 1 mips ec mode dc20a 4 ma 25c dc20b ma 85c dc20c ma 125c dc20d ma -40c 5v dc20e 7 ma 25c dc20f ma 85c dc20g ma 125c dc23 ma -40c 3.3v 4 mips ec mode, 4x pll dc23a 13 ma 25c dc23b ma 85c dc23c ma 125c dc23d ma -40c 5v dc23e 22 ma 25c dc23f ma 85c dc23g ma 125c dc24 ma -40c 3.3v 10 mips ec mode, 4x pll dc24a 29 ma 25c dc24b ma 85c dc24c ma 125c dc24d ma -40c 5v dc24e 50 ma 25c dc24f ma 85c dc24g ma 125c dc25 ma -40c 3.3v 8 mips ec mode, 8x pll dc25a 23 ma 25c dc25b ma 85c dc25c ma 125c dc25d ma -40c 5v dc25e 41 ma 25c dc25f ma 85c dc25g ma 125c note 1: data in typical column is at 5v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 2: the supply current is mainly a function of the operatin g voltage and frequency. ot her factors such as i/o pin loading and switching rate, oscillator type, inter nal code execution pattern and temperature also have an impact on the current consumpt ion. the test co nditions for all i dd measurements are as follows: osc1 driven with external square wave fr om rail to rail. all i/o pins are configured as inputs and pulled to v dd . mclr = v dd , wdt, fscm, lvd and bor are disabled. cpu, sram, program memory and data memory are operational. no per ipheral modules are operating.
dspic30f ds70083g-page 186 preliminary ? 2004 microchip technology inc. dc27 ma -40c 3.3v 20 mips ec mode, 8x pll dc27a 50 ma 25c dc27b ma 85c dc27c ma -40c 5v dc27d 90 ma 25c dc27e ma 85c dc27f ma 125c dc28 ma -40c 3.3v 16 mips ec mode, 16x pll dc28a 42 ma 25c dc28b ma 85c dc28c ma -40c 5v dc28d 76 ma 25c dc28e ma 85c dc28f ma 125c dc29 ma -40c 5v 30 mips ec mode, 16x pll dc29a 146 ma 25c dc29b ma 85c dc29c ma 125c dc30 ma -40c 3.3v frc (~ 2 mips) dc30a 7.0 ma 25c dc30b ma 85c dc30c ma 125c dc30d ma -40c 5v dc30e 12 ma 25c dc30f ma 85c dc30g ma 125c dc31 ma -40c 3.3v lprc (~ 512 khz) dc31a 1.5 ma 25c dc31b ma 85c dc31c ma 125c dc31d ma -40c 5v dc31e 2.5 ma 25c dc31f ma 85c dc31g ma 125c table 23-3: dc characteristics: operating current (i dd ) (continued) dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions operating current (i dd ) (2) note 1: data in typical column is at 5v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 2: the supply current is mainly a function of the operatin g voltage and frequency. other factors such as i/o pin loading and switching rate, oscillat or type, internal code execution pattern and temperature also have an impact on the current consumption. the test conditions for all i dd measurements are as follows: osc1 driven with external square wave from rail to rail. all i/o pins are co nfigured as inputs and pulled to v dd . mclr = v dd , wdt, fscm, lvd and bor are disabled. cpu, sram, program memory and data memory are operational. no per ipheral modules are operating.
? 2004 microchip technology inc. preliminary ds70083g-page 187 dspic30f table 23-4: dc characteristics: idle current (i idle ) dc characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions idle current (i idle ): core off clock on base current (2) dc40 ma -40c 3.3v 1 mips ec mode dc40a 3 ma 25c dc40b ma 85c dc40c ma 125c dc40d ma -40c 5v dc40e 5 ma 25c dc40f ma 85c dc40g ma 125c dc43 ma -40c 3.3v 4 mips ec mode, 4x pll dc43a 7.7 ma 25c dc43b ma 85c dc43c ma 125c dc43d ma -40c 5v dc43e 13 ma 25c dc43f ma 85c dc43g ma 125c dc44 ma -40c 3.3v 10 mips ec mode, 4x pll dc44a 15 ma 25c dc44b ma 85c dc44c ma 125c dc44d ma -40c 5v dc44e 29 ma 25c dc44f ma 85c dc44g ma 125c dc45 ma -40c 3.3v 8 mips ec mode, 8x pll dc45a 13 ma 25c dc45b ma 85c dc45c ma 125c dc45d ma -40c 5v dc45e 24 ma 25c dc45f ma 85c dc45g ma 125c note 1: data in typical column is at 5v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 2: base i idle current is measured with core off, clock on an d all modules turned off.
dspic30f ds70083g-page 188 preliminary ? 2004 microchip technology inc. dc47 ma -40c 3.3v 20 mips ec mode, 8x pll dc47a 29 ma 25c dc47b ma 85c dc47c ma -40c 5v dc47d 52 ma 25c dc47e ma 85c dc47f ma 125c dc48 ma -40c 3.3v 16 mips ec mode, 16x pll dc48a 24 ma 25c dc48b ma 85c dc48c ma -40c 5v dc48d 43 ma 25c dc48e ma 85c dc48f ma 125c dc49 ma -40c 5v 30 mips ec mode, 16x pll dc49a 73 ma 25c dc49b ma 85c dc49c ma 125c dc50 ma -40c 3.3v frc (~ 2 mips) dc50a 4.0 ma 25c dc50b ma 85c dc50c ma 125c dc50d ma -40c 5v dc50e 7.0 ma 25c dc50f ma 85c dc50g ma 125c dc51 ma -40c 3.3v lprc (~ 512 khz) dc51a 1.0 ma 25c dc51b ma 85c dc51c ma 125c dc51d ma -40c 5v dc51e 1.5 ma 25c dc51f ma 85c dc51g ma 125c table 23-4: dc characteristics: idle current (i idle ) (continued) dc characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions idle current (i idle ): core off clock on base current (2) note 1: data in typical column is at 5v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 2: base i idle current is measured with core off, clock on and all modules turned off.
? 2004 microchip technology inc. preliminary ds70083g-page 189 dspic30f table 23-5: dc characteristics: power-down current (i pd ) dc characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions power down current (i pd ) (2) dc60 a -40c 3.3v base power down current (3) dc60a 0.1 a25c dc60b a85c dc60c a 125c dc60d a -40c 5v dc60e 0.2 a25c dc60f a85c dc60g a 125c dc61 a -40c 3.3v watchdog timer current: ? i wdt (3) dc61a 6.8 a25c dc61b a85c dc61c a 125c dc61d a -40c 5v dc61e 16 a25c dc61f a85c dc61g a 125c dc62 a -40c 3.3v timer 1 w/32 khz crystal: ? i ti 32 (3) dc62a 5.5 a25c dc62b a85c dc62c a 125c dc62d a -40c 5v dc62e 7.5 a25c dc62f a85c dc62g a 125c dc63 a -40c 3.3v bor on: ? i bor (3) dc63a 32 a25c dc63b a85c dc63c a 125c dc63d a -40c 5v dc63e 38 a25c dc63f a85c dc63g a 125c note 1: data in the typical column is at 5v, 25c unless otherwise stated. paramete rs are for design guidance only and are not tested. 2: base i pd is measured with all peripherals and clocks shut down. all i/os are configured as inputs and pulled high. lvd, bor, wdt, etc. are all switched off. 3: the ? current is the additional curren t consumed when the module is e nabled. this current should be added to the base i pd current.
dspic30f ds70083g-page 190 preliminary ? 2004 microchip technology inc. dc66 a-40c 3.3v low voltage detect: ? i lvd (3) dc66a 25 a 25c dc66b a 85c dc66c a125c dc66d a-40c 5v dc66e 30 a 25c dc66f a 85c dc66g a125c table 23-5: dc characteristics: power-down current (i pd ) (continued) dc characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended parameter no. typical (1) max units conditions power down current (i pd ) (2) note 1: data in the typical column is at 5v, 25c unless otherwise stated. pa rameters are for design guidance only and are not tested. 2: base i pd is measured with all peripher als and clocks shut do wn. all i/os are configured as inputs and pulled high. lvd, bor, wdt, etc. are all switched off. 3: the ? current is the additional current consumed wh en the module is enabled. this current should be added to the base i pd current.
? 2004 microchip technology inc. preliminary ds70083g-page 191 dspic30f table 23-6: dc characteristics: i/o pin input specifications dc characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions v il input low voltage (2) di10 i/o pins: with schmitt trigger buffer v ss 0.2v dd v di15 mclr v ss 0.2v dd v di16 osc1 (in xt, hs and lp modes) v ss 0.2v dd v di17 osc1 (in rc mode) (3) v ss 0.3v dd v di18 sda, scl tbd tbd v sm bus disabled di19 sda, scl tbd tbd v sm bus enabled v ih input high voltage (2) di20 i/o pins: with schmitt trigger buffer 0.8 v dd v dd v di25 mclr 0.8 v dd v dd v di26 osc1 (in xt, hs and lp modes) 0.7 v dd v dd v di27 osc1 (in rc mode) (3) 0.9 v dd v dd v di28 sda, scl tbd tbd v sm bus disabled di29 sda, scl tbd tbd v sm bus enabled i cnpu cn xx pull-up current (2) di30 50 250 400 av dd = 5v, v pin = v ss di31 tbd tbd tbd av dd = 3v, v pin = v ss i il input leakage current (2)(4)(5) di50 i/o ports 0.01 1 av ss v pin v dd , pin at hi-impedance di51 analog input pins 0.50 av ss v pin v dd , pin at hi-impedance di55 mclr 0.055 av ss v pin v dd di56 osc1 0.05 5 av ss v pin v dd , xt, hs and lp osc mode note 1: data in typ column is at 5v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. 3: in rc oscillator configuration, the osc1/clkl pin is a schmitt trigger input. it is not recommended that the dspic30f device be driven with an external clock while in rc mode. 4: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal oper ating conditions. higher leakage curren t may be measured at different input voltages. 5: negative current is defined as current sourced by the pin.
dspic30f ds70083g-page 192 preliminary ? 2004 microchip technology inc. figure 23-1: low-voltage detect characteristics table 23-7: dc characteristics: i/o pin output specifications dc characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions v ol output low voltage (2) do10 i/o ports 0.6 v i ol = 8.5 ma, v dd = 5v tbdvi ol = 2.0 ma, v dd = 3v do16 osc2/clkout 0.6 v i ol = 1.6 ma, v dd = 5v (rc or ec osc mode) tbd v i ol = 2.0 ma, v dd = 3v v oh output high voltage (2) do20 i/o ports v dd C 0.7 v i oh = -3.0 ma, v dd = 5v tbd v i oh = -2.0 ma, v dd = 3v do26 osc2/clkout v dd C 0.7 v i oh = -1.3 ma, v dd = 5v (rc or ec osc mode) tbd v i oh = -2.0 ma, v dd = 3v capacitive loading specs on output pins (2) do50 c osco osc2/sosco pin 15 pf in xtl, xt, hs and lp modes when external clock is used to drive osc1. do56 c io all i/o pins and osc2 50 pf rc or ec osc mode do58 c b scl, sda 400 pf in i 2 c mode note 1: data in typ column is at 5v, 25c unless otherwis e stated. parameters are fo r design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. lv10 lvdif v dd (lvdif set by hardware)
? 2004 microchip technology inc. preliminary ds70083g-page 193 dspic30f table 23-8: electrical characteristics: lvdl figure 23-2: brown-out reset characteristics dc characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions lv10 v plvd lvdl voltage on v dd transition high to low lvdl = 0000 (2) v lvdl = 0001 (2) v lvdl = 0010 (2) v lvdl = 0011 (2) v lvdl = 0100 2.50 2.65 v lvdl = 0101 2.70 2.86 v lvdl = 0110 2.80 2.97 v lvdl = 0111 3.00 3.18 v lvdl = 1000 3.30 3.50 v lvdl = 1001 3.50 3.71 v lvdl = 1010 3.60 3.82 v lvdl = 1011 3.80 4.03 v lvdl = 1100 4.00 4.24 v lvdl = 1101 4.20 4.45 v lvdl = 1110 4.50 4.77 v lv15 v lvdin external lvd input pin threshold voltage lvdl = 1111 v note 1: these parameters are characterize d but not tested in manufacturing. 2: these values not in us able operating range. bo10 reset (due to bor) v dd (device in brown-out reset) (device not in brown-out reset) power up time-out bo15
dspic30f ds70083g-page 194 preliminary ? 2004 microchip technology inc. table 23-9: electrical characteristics: bor table 23-10: dc characteristics: program and eeprom dc characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions bo10 v bor bor voltage (2) on v dd transition high to low borv = 00 (3) v not in operating range borv = 01 2.7 2.86 v borv = 10 4.2 4.46 v borv = 11 4.5 4.78 v bo15 v bhys 5mv note 1: data in typ column is at 5v, 25c unless otherwis e stated. parameters are fo r design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. 3: 00 values not in usable operating range. dc characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions data eeprom memory (2) d120 e d byte endurance 100k 1m e/w -40 c t a +85c d121 v drw v dd for read/write v min 5.5 v using nvmcon to read/write v min = minimum operating voltage d122 t dew erase/write cycle time 2 ms d123 t retd characteristic retention 40 100 yea r provided no other specifications are violated d124 i dew i dd during programming 10 30 ma row erase program flash memory (2) d130 e p cell endurance 10k 100k e/w -40 c t a +85c d131 v pr v dd for read v min 5.5vv min = minimum operating voltage d132 v eb v dd for bulk erase 3.0 5.5 v d133 v pew v dd for erase/write 3.0 5.5 v d134 t pew erase/write cycle time 2 ms d135 t retd characteristic retention 40 100 yea r provided no other specifications are violated d136 t eb icsp block erase time 4 ms d137 i pew i dd during programming 10 30 ma row erase d138 i eb i dd during programming 10 30 ma bulk erase note 1: data in typ column is at 5v , 25c unless otherwise stated. 2: these parameters are characterized but not tested in manufacturing.
? 2004 microchip technology inc. preliminary ds70083g-page 195 dspic30f 23.2 ac characteristics and timing parameters the information contained in this section defines dspic30f ac charac teristics and timi ng parameters. table 23-11: temperature and voltage specifications ? ac figure 23-3: load conditions for device timing specifications figure 23-4: external clock timing ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended operating voltage v dd range as described in dc spec section 23.0. v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2 5 pf for osc2 output load condition 1 - for all pins except osc2 load condition 2 - for osc2 osc1 clkout q4 q1 q2 q3 q4 q1 os20 os25 os30 os30 os40 os41 os31 os31
dspic30f ds70083g-page 196 preliminary ? 2004 microchip technology inc. table 23-12: external clock timing requirements ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions os10 f osc external clkin frequency (2) (external clocks allowed only in ec mode) dc 4 4 4 40 10 10 7.5 mhz mhz mhz mhz ec ec with 4x pll ec with 8x pll ec with 16x pll oscillator frequency (2) dc 0.4 4 4 4 4 10 31 8 512 4 4 10 10 10 7.5 25 33 mhz mhz mhz mhz mhz mhz mhz khz mhz khz rc xtl xt xt with 4x pll xt with 8x pll xt with 16x pll hs lp frc internal lprc internal os20 t osc t osc = 1/f osc see parameter os10 for f osc value os25 t cy instruction cycle time (2)(3) 33 dc ns see table 23-14 os30 tosl, to s h external clock (2) in (osc1) high or low time .45 x t osc nsec os31 tosr, to s f external clock (2) in (osc1) rise or fall time 20 ns ec os40 tckr clkout rise time (2)(4) 6 10 ns os41 tckf clkout fall time (2)(4) 6 10 ns note 1: data in typ column is at 5v, 25 c unless otherwise stated. paramete rs are for design guidance only and are not tested. 2: these parameters are characterized but not tested in manufacturing. 3: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under st andard operating conditions with the device executing code. exceeding these spe cified limits may result in an unstable oscillator operation and/or higher than expect ed current consumption. all devices ar e tested to operate at min. values with an external clock appl ied to the osc1/clki pin. when an external clock input is used, the max. cycle time limit is dc (no clock) for all devices. 4: measurements are taken in ec or erc modes. the clkout signal is measured on the osc2 pin. clkout is low for the q1-q2 period (1/2 t cy ) and high for the q3-q4 period (1/2 t cy ).
? 2004 microchip technology inc. preliminary ds70083g-page 197 dspic30f table 23-14: internal clock timing examples table 23-13: pll clock timing specifications (v dd = 2.5 to 5.5 v) ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions os50 f plli pll input frequency range (2) 4 10 mhz ec, xt modes with pll os51 f sys on-chip pll output (2) 16 120 mhz ec, xt modes with pll os52 t loc pll start-up time (lock time) 20 50 s os53 d clk clkout stability (jitter) tbd 1 tbd % measured over 100 ms period note 1: these parameters are characterize d but not tested in manufacturing. 2: data in typ column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. clock oscillator mode f osc (mhz) (1) t cy ( sec) (2) mips (3) w/o pll mips (3) w pll x4 mips (3) w pll x8 mips (3) w pll x16 ec 0.200 20.0 0.05 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 25 0.16 25.0 xt 4 1.0 1.0 4.0 8.0 16.0 10 0.4 2.5 10.0 20.0 note 1: assumption: oscillator po stscaler is divide by 1. 2: instruction execution cycle time: t cy = 1 / mips. 3: instruction execution frequency: mips = (f osc * pllx) / 4 [since there are 4 q clocks per instruction cycle]. table 23-15: internal rc accuracy ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. characteristic min typ max units conditions frc @ freq = 8 mhz (1) f16 tbd tbd % -40c to +85c v dd =3.3v f19 tbd tbd % -40c to +85c v dd =5v lprc @ freq = 512 khz (2) f20 tbd tbd % -40c to +85c v dd =3v f21 tbd tbd % -40c to +85c v dd =5v note 1: frequency calibrated at 25c and 5v. tun bits can be used to compensat e for temperature drift. 2: lprc frequency after calibration. 3: change of lprc frequency as v dd changes.
dspic30f ds70083g-page 198 preliminary ? 2004 microchip technology inc. figure 23-5: clkout and i/o timing characteristics table 23-16: clkout and i/o timing requirements ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1)(2)(3) min typ (4) max units conditions do31 t io r port output rise time 10 25 ns do32 t io f port output fall time 10 25 ns di35 t inp intx pin high or low time (output) 20 ns di40 t rbp cnx high or low time (input) 2 t cy ns note 1: these parameters are asynchronous event s not related to any internal clock edges 2: measurements are taken in rc mode an d ec mode where clkout output is 4 x t osc . 3: these parameters are characterized but not tested in manufacturing. 4: data in typ column is at 5v , 25c unless otherwise stated. note: refer to figure 23-3 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32
? 2004 microchip technology inc. preliminary ds70083g-page 199 dspic30f figure 23-6: reset, watchdog timer, osci llator start-up timer and power-up timer timing characteristics v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset sy11 sy10 sy20 sy13 i/o pins sy13 note: refer to figure 23-3 for load conditions. fscm delay sy35 sy30 sy12
dspic30f ds70083g-page 200 preliminary ? 2004 microchip technology inc. table 23-17: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset timing requirements figure 23-7: band gap start-up time characteristics table 23-18: band gap start-up time requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sy10 tmcl mclr pulse width (low) 2 s -40c to +85c sy11 t pwrt power-up timer period tbd tbd tbd tbd 0 4 16 64 tbd tbd tbd tbd ms -40c to +85c user programmable sy12 t por power on reset delay 3 10 30 s -40c to +85c sy13 t ioz i/o hi-impedance from mclr low or watchdog timer reset 100ns sy20 t wdt 1 watchdog timer time-out period (no prescaler) 1.8 2.0 2.2 ms v dd = 5v, -40c to +85c t wdt 2 1.9 2.1 2.3 ms v dd = 3v, -40c to +85c sy25 t bor brown-out reset pulse width (3) 100 sv dd v bor (d034) sy30 t ost oscillation start-up timer period 1024 t osc t osc = osc1 period sy35 t fscm fail-safe clock monitor delay 100 s -40c to +85c note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 5v , 25c unless otherwise stated. 3: refer to figure 23-2 and table 23-9 for bor. ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sy40 t bgap band gap start-up time 20 50 s defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable. rcon<13>status bit note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 5v , 25c unless otherwise stated. v bgap enable band gap band gap 0v (see note) stable note: set lvden bit (rcon<12>) or fborpor<7>set. sy40
? 2004 microchip technology inc. preliminary ds70083g-page 201 dspic30f figure 23-8: type a, b and c timer externa l clock timing characteristics table 23-19: type a timer (timer1) extern al clock timing requirements ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ max units conditions ta10 t tx h txck high time synchronous, no prescaler 0.5 t cy + 20 ns must also meet parameter ta15 synchronous, with prescaler 10 ns asynchronous 10 ns ta11 t tx l txck low time synchronous, no prescaler 0.5 t cy + 20 ns must also meet parameter ta15 synchronous, with prescaler 10 ns asynchronous 10 ns ta15 t tx p txck input period synchronous, no prescaler t cy + 10 ns synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n n = prescale value (1, 8, 64, 256) asynchronous 20 ns os60 ft1 sosci/t1ck oscillator input frequency range (o scillator enabled by setting bit tcs (t1con, bit 1)) dc 50 khz ta20 t ckextmrl delay from external tqck clock edge to timer increment 2 t osc 6 t osc note: timer1 is a type a. note: refer to figure 23-3 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck
dspic30f ds70083g-page 202 preliminary ? 2004 microchip technology inc. table 23-20: type b timer (timer2 and timer4) external clock timing requirements table 23-21: type c timer (timer3 and timer5 ) external clock timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ max units conditions tb10 ttxh txck high time synchronous, no prescaler 0.5 t cy + 20 ns must also meet parameter tb15 synchronous, with prescaler 10 ns tb11 ttxl txck low time synchronous, no prescaler 0.5 t cy + 20 ns must also meet parameter tb15 synchronous, with prescaler 10 ns tb15 ttxp txck input period synchronous, no prescaler t cy + 10 ns n = prescale value (1, 8, 64, 256) synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n tb20 t ckextmrl delay from external tqck clock edge to timer increment 2 t osc 6 t osc note: timer2 and timer4 are type b. ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min typ max units conditions tc10 ttxh txck high time synchronous 0.5 t cy + 20 ns must also meet parameter tc15 tc11 ttxl txck low time synchronous 0.5 t cy + 20 ns must also meet parameter tc15 tc15 ttxp txck input period synchronous, no prescaler t cy + 10 ns n = prescale value (1, 8, 64, 256) synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n tc20 t ckextmrl delay from external tqck clock edge to timer increment 2 t osc 6 t osc note: timer3 and timer5 are type c.
? 2004 microchip technology inc. preliminary ds70083g-page 203 dspic30f figure 23-9: input capture (capx) timing characteristics table 23-22: input capture timi ng requirements figure 23-10: output compare module (ocx) timing characteristics table 23-23: output compare module timing requirements ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min max units conditions ic10 tccl icx input low time no prescaler 0.5 t cy + 20 ns with prescaler 10 ns ic11 tcch icx input high time no prescaler 0.5 t cy + 20 ns with prescaler 10 ns ic15 tccp icx input period (2 t cy + 40)/n ns n = prescale value (1, 4, 16) note 1: these parameters are characterize d but not tested in manufacturing. ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions oc10 tccf ocx output fall time 10 25 ns oc11 tccr ocx output rise time 10 25 ns note 1: these parameters are characterize d but not tested in manufacturing. 2: data in typ column is at 5v, 25c unless otherw ise stated. parameters are for design guidance only and are not tested. ic x ic10 ic11 ic15 note: refer to figure 23-3 for load conditions. ocx oc11 oc10 (output compare note: refer to figure 23-3 for load conditions. or pwm mode)
dspic30f ds70083g-page 204 preliminary ? 2004 microchip technology inc. figure 23-11: oc/pwm module timing characteristics table 23-24: simple oc/pwm mode timing requirements ac characteristics standard operating cond itions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions oc15 t fd fault input to pwm i/o change 25 ns v dd = 3v -40c to +85c tbd ns v dd = 5v oc20 t flt fault input pulse width 50 ns v dd = 3v -40c to +85c tbd ns v dd = 5v note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 5v, 25c unless otherwis e stated. parameters are fo r design guidance only and are not tested. ocfa/ocfb ocx oc20 oc15
? 2004 microchip technology inc. preliminary ds70083g-page 205 dspic30f figure 23-12: dci module (multichannel, i 2 s modes) timing characteristics cofs csck (scke = 1 ) csck (scke = 0 ) csdo csdi cs11 cs10 cs40 cs41 cs21 cs20 cs35 cs21 msb lsb msb in lsb in cs31 high-z high-z 70 cs30 cs51 cs50 cs55 note: refer to figure 23- 3 for load conditions. cs20 cs56
dspic30f ds70083g-page 206 preliminary ? 2004 microchip technology inc. table 23-25: dci module (multichannel, i 2 s modes) timing requirements ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions cs10 tc sckl csck input low time (csck pin is an input) t cy / 2 + 20 ns csck output low time (3) (csck pin is an output) 30 ns cs11 tc sckh csck input high time (csck pin is an input) t cy / 2 + 20 ns csck output high time (3) (csck pin is an output) 30 ns cs20 tc sckf csck output fall time (4) (csck pin is an output) 1025ns cs21 tc sckr csck output rise time (4) (csck pin is an output) 1025ns cs30 tc sdof csdo data output fall time (4) 1025ns cs31 tc sdor csdo data output rise time (4) 1025ns cs35 t dv clock edge to csdo data valid 10 ns cs36 t div clock edge to csdo tri-stated 10 20 ns cs40 t csdi setup time of csdi data input to csck edge (csck pin is input or output) 20 ns cs41 t hcsdi hold time of csdi data input to csck edge (csck pin is input or output) 20 ns cs50 tco fsf cofs fall time (cofs pin is output) 1025ns note 1 cs51 tco fsr cofs rise time (cofs pin is output) 1025ns note 1 cs55 tsco fs setup time of cofs data input to csck edge (cofs pin is input) 20 ns cs56 t hcofs hold time of cofs data input to csck edge (cofs pin is input) 20 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. 3: the minimum clock period for csck is 100 ns. therefore, the clock ge nerated in master mode must not violate this specification. 4: assumes 50 pf load on all dci pins.
? 2004 microchip technology inc. preliminary ds70083g-page 207 dspic30f figure 23-13: dci module (ac-link mode) timing characteristics table 23-26: dci module (ac-link mode) timing requirements ac characteristics standard operating condi tions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1)(2) min typ (3) max units conditions cs60 t bclkl bit_clk low time 36 40.7 45 ns cs61 t bclkh bit_clk high time 36 40.7 45 ns cs62 t bclk bit_clk period 81.4 ns bit clock is input cs65 t sacl input setup time to falling edge of bit_clk 10 ns cs66 t hacl input hold time from falling edge of bit_clk 10 ns cs70 t synclo sync data output low time 19.5 s note 1 cs71 t synchi sync data output high time 1.3 s note 1 cs72 t sync sync data output period 20.8 s note 1 cs75 t racl rise time, sync, sdata_out 10 25 ns c load = 50 pf, v dd = 5v cs76 t facl fall time, sync, sdata_out 10 25 ns c load = 50 pf, v dd = 5v cs77 t racl rise time, sync, sdata_out tbd tbd ns c load = 50 pf, v dd = 3v cs78 t facl fall time, sync, sdata_out tbd tbd ns c load = 50 pf, v dd = 3v cs80 t ovdacl output valid delay from rising edge of bit_clk 15 ns note 1: these parameters are characterize d but not tested in manufacturing. 2: these values assume bit_cl k frequency is 12.288 mhz. 3: data in typ column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. sync bit_clk sdo sdi cs61 cs60 cs65 cs66 cs80 cs21 msb in cs75 lsb cs76 (cofs) (csck) lsb msb cs72 cs71 cs70 cs76 cs75 (csdo) (csdi) cs62 cs20
dspic30f ds70083g-page 208 preliminary ? 2004 microchip technology inc. figure 23-14: spi module master mode (cke = 0 ) timing characteristics table 23-27: spi master mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscl sck x output low time (3) t cy / 2 ns sp11 tsch sck x output high time (3) t cy / 2 ns sp20 tscf sck x output fall time (4 1025ns sp21 tscr sck x output rise time (4) 1025ns sp30 tdof sdo x data output fall time (4) 1025ns sp31 tdor sdo x data output rise time (4) 1025ns sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ns sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 5v, 25c unless otherwis e stated. parameters are fo r design guidance only and are not tested. 3: the minimum clock period for sck is 100 ns. therefore, the clock ge nerated in master mode must not violate this specification. 4: assumes 50 pf load on all spi pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp11 sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit14 - - - - - -1 msb in lsb in bit14 - - - -1 sp30 sp31 note: refer to figure 23-3 for load conditions.
? 2004 microchip technology inc. preliminary ds70083g-page 209 dspic30f figure 23-15: spi module master mode (cke = 1 ) timing characteristics table 23-28: spi module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscl sck x output low time (3) t cy / 2 ns sp11 tsch sck x output high time (3) t cy / 2 ns sp20 tscf sck x output fall time (4) 1025ns sp21 tscr sck x output rise time (4) 1025ns sp30 tdof sdo x data output fall time (4) 1025ns sp31 tdor sdo x data output rise time (4) 1025ns sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge 30 ns sp36 tdov2sc, tdov2scl sdo x data output setup to first sck x edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ns sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ns note 1: these parameters are characterize d but not tested in manufacturing. 2: data in typ column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. 3: the minimum clock period for sck is 100 ns. therefore, the clock g enerated in master mode must not violate this specification. 4: assumes 50 pf load on all spi pins. sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi x sp36 sp30,sp31 sp35 msb msb in bit14 - - - - - -1 lsb in bit14 - - - -1 lsb note: refer to figure 23-3 for load conditions. sp11 sp10 sp20 sp21 sp21 sp20 sp40 sp41
dspic30f ds70083g-page 210 preliminary ? 2004 microchip technology inc. figure 23-16: spi module slave mode (cke = 0 ) timing characteristics table 23-29: spi module slave mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscl sck x input low time 30 ns sp71 tsch sck x input high time 30 ns sp20 tscf sck x output fall time (3) 1025ns sp21 tscr sck x output rise time (3) 1025ns sp30 tdof sdo x data output fall time (3) 1025ns sp31 tdor sdo x data output rise time (3) 1025ns sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ns sp41 tsch2dil, tscl2dil hold time of sdi x data input to sck x edge 20 ns sp50 tssl2sch, tssl2scl ss x to sck x or sck x input 120 ns sp51 tssh2doz ss x to sdo x output hi-impedance (3) 10 50 ns sp52 tsch2ssh tscl2ssh ss x after sck edge 1.5 t cy +40 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 5v, 25c unless otherwis e stated. parameters are fo r design guidance only and are not tested. 3: assumes 50 pf load on all spi pins. ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi sp50 sp40 sp41 sp30,sp31 sp51 sp35 sdi x msb lsb bit14 - - - - - -1 msb in bit14 - - - -1 lsb in sp52 sp21 sp20 sp21 sp20 sp71 sp70 note: refer to figure 23-3 for load conditions.
? 2004 microchip technology inc. preliminary ds70083g-page 211 dspic30f figure 23-17: spi module slave mode (cke = 1 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi sp50 sp60 sdi x sp30,sp31 msb bit14 - - - - - -1 lsb sp51 msb in bit14 - - - -1 lsb in sp35 sp52 sp52 sp21 sp20 sp21 sp20 sp71 sp70 sp40 sp41 note: refer to figure 23-3 for load conditions.
dspic30f ds70083g-page 212 preliminary ? 2004 microchip technology inc. table 23-30: spi module slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 ts c l sck x input low time 30 ns sp71 tsch sck x input high time 30 ns sp20 tscf sck x output fall time (3) 1025ns sp21 tscr sck x output rise time (3) 1025ns sp30 tdof sdo x data output fall time (3) 1025ns sp31 tdor sdo x data output rise time (3) 1025ns sp35 tsch2dov, tscl2dov sdo x data output valid after sck x edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdi x data input to sck x edge 20 ns sp41 tsch2dil, ts c l 2 d i l hold time of sdi x data input to sck x edge 20 ns sp50 tssl2sch, tssl2scl ss x to sck x or sck x input 120 ns sp51 tssh2doz ss to sdo x output hi-impedance (4) 10 50 ns sp52 tsch2ssh tscl2ssh ss x after sck x edge 1.5 t cy + 40 ns sp60 tssl2dov sdo x data output valid after ss x edge 50 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. 3: the minimum clock period for sck is 100 ns. therefore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spi pins.
? 2004 microchip technology inc. preliminary ds70083g-page 213 dspic30f figure 23-18: i 2 c bus start/stop bits timing characteristics (master mode) figure 23-19: i 2 c bus data timing characteristics (master mode) im31 im34 scl sda start condition stop condition im30 im33 note: refer to figure 23-3 for load conditions. im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 scl sda in sda out note: refer to figure 23-3 for load conditions.
dspic30f ds70083g-page 214 preliminary ? 2004 microchip technology inc. table 23-31: i 2 c bus data timing requirements (master mode) ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min (1) max units conditions im10 t lo : scl clock low time 100 khz mode t cy / 2 (brg + 1) ms 400 khz mode t cy / 2 (brg + 1) ms 1 mhz mode (2) t cy / 2 (brg + 1) ms im11 t hi : scl clock high time 100 khz mode t cy / 2 (brg + 1) ms 400 khz mode t cy / 2 (brg + 1) ms 1 mhz mode (2) t cy / 2 (brg + 1) ms im20 t f : scl sda and scl fall time 100 khz mode 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) 100ns im21 t r : scl sda and scl rise time 100 khz mode 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) 300ns im25 t su : dat data input setup time 100 khz mode 250 ns 400 khz mode 100 ns 1 mhz mode (2) tbd ns im26 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 ms 1 mhz mode (2) tbd ns im30 t su : sta start condition setup time 100 khz mode t cy / 2 (brg + 1) ms only relevant for repeated start condition 400 khz mode t cy / 2 (brg + 1) ms 1 mhz mode (2) t cy / 2 (brg + 1) ms im31 t hd : sta start condition hold time 100 khz mode t cy / 2 (brg + 1) ms after this period the first clock pulse is generated 400 khz mode t cy / 2 (brg + 1) ms 1 mhz mode (2) t cy / 2 (brg + 1) ms im33 t su : sto stop condition setup time 100 khz mode t cy / 2 (brg + 1) ms 400 khz mode t cy / 2 (brg + 1) ms 1 mhz mode (2) t cy / 2 (brg + 1) ms im34 t hd : sto stop condition 100 khz mode t cy / 2 (brg + 1) ns hold time 400 khz mode t cy / 2 (brg + 1) ns 1 mhz mode (2) t cy / 2 (brg + 1) ns im40 t aa : scl output valid from clock 100 khz mode 3500 ns 400 khz mode 1000 ns 1 mhz mode (2) ns im45 t bf : sda bus free time 100 khz mode 4.7 ms time the bus must be free before a new transmission can start 400 khz mode 1.3 ms 1 mhz mode (2) tbd ms im50 c b bus capacitive loading 400 pf note 1: brg is the value of the i 2 c baud rate generator. refer to section 21 ?inter-integrated circuit? (i 2 c)? in the dspic30f family reference manual. 2: maximum pin capacitance = 10 pf for all i 2 c pins (for 1 mhz mode only).
? 2004 microchip technology inc. preliminary ds70083g-page 215 dspic30f figure 23-20: i 2 c bus start/stop bits timing characteristics (slave mode) figure 23-21: i 2 c bus data timing characteristics (slave mode) is31 is34 scl sda start condition stop condition is30 is33 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 scl sda in sda out
dspic30f ds70083g-page 216 preliminary ? 2004 microchip technology inc. table 23-32: i 2 c bus data timing requirements (slave mode) ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min max units conditions is10 t lo : scl clock low time 100 khz mode 4.7 s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 s device must operate at a minimum of 10 mhz. 1 mhz mode (1) 0.5 s is11 t hi : scl clock high time 100 khz mode 4.0 s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 s device must operate at a minimum of 10 mhz 1 mhz mode (1) 0.5 s is20 t f : scl sda and scl fall time 100 khz mode 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) 100 ns is21 t r : scl sda and scl rise time 100 khz mode 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) 300 ns is25 t su : dat data input setup time 100 khz mode 250 ns 400 khz mode 100 ns 1 mhz mode (1) 100 ns is26 t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 s 1 mhz mode (1) 00.3 s is30 t su : sta start condition setup time 100 khz mode 4.7 s only relevant for repeated start condition 400 khz mode 0.6 s 1 mhz mode (1) 0.25 s is31 t hd : sta start condition hold time 100 khz mode 4.0 s after this period the first clock pulse is generated 400 khz mode 0.6 s 1 mhz mode (1) 0.25 s is33 t su : sto stop condition setup time 100 khz mode 4.7 s 400 khz mode 0.6 s 1 mhz mode (1) 0.6 s is34 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 ns 1 mhz mode (1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns 400 khz mode 0 1000 ns 1 mhz mode (1) 0 350 ns is45 t bf : sda bus free time 100 khz mode 4.7 s time the bus must be free before a new transmission can start 400 khz mode 1.3 s 1 mhz mode (1) 0.5 s is50 c b bus capacitive loading 400pf note 1: maximum pin capacitance = 10 pf for all i 2 c pins (for 1 mhz mode only).
? 2004 microchip technology inc. preliminary ds70083g-page 217 dspic30f figure 23-22: can module i/o timing characteristics table 23-33: can module i/o timing requirements ac characteristics standard operating conditions: 2.5v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions ca10 tiof port output fall time 10 25 ns ca11 tior port output rise time 10 25 ns ca20 tcwf pulse width to trigger can wakeup filter 500 ns note 1: these parameters are characterize d but not tested in manufacturing. 2: data in typ column is at 5v, 25c unless otherwise stated. parameters are fo r design guidance only and are not tested. c x t x pin (output) ca10 ca11 old value new value ca20 c x r x pin (input)
dspic30f ds70083g-page 218 preliminary ? 2004 microchip technology inc. table 23-34: 12-bit a/d module specifications ac characteristics standard operating condi tions: 2.7v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min. typ max. units conditions device supply ad01 av dd module v dd supply greater of v dd - 0.3 or 2.7 lesser of v dd + 0.3 or 5.5 v ad02 av ss module v ss supply v ss - 0.3 v ss + 0.3 v reference inputs ad05 v refh reference voltage high av ss + 2.7 av dd v ad06 v refl reference voltage low av ss av dd - 2.7 v ad07 v ref absolute reference voltage av ss - 0.3 av dd + 0.3 v ad08 i ref current drain 200 .001 300 3 a a a/d operating a/d off analog input ad10 v inh -v inl full-scale input span v refl v refh v see note ad11 v in absolute input voltage av ss - 0.3 av dd + 0.3 v ad12 leakage current 0.001 0.610 av inl = av ss = v refl = 0v, av dd = v refh = 5v source impedance = 2.5 k ? ad13 leakage current 0.001 0.610 av inl = av ss = v refl = 0v, av dd = v refh = 3v source impedance = 2.5 k ? ad15 r ss switch resistance 3.2k ? ad16 c sample sample capacitor 18 pf ad17 r in recommended impedance of analog voltage source 2.5k ? dc accuracy ad20 nr resolution 12 data bits bits ad21 inl integral nonlinearity 0.75 tbd lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad21a inl integral nonlinearity 0.75 tbd lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad22 dnl differential nonlinearity 0.5 < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad22a dnl differential nonlinearity 0.5 < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad23 g err gain error 1.25 tbd lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad23a g err gain error 1.25 tbd lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v note 1: the a/d conversion result never decreases with an increase in the input vo ltage, and has no missing codes.
? 2004 microchip technology inc. preliminary ds70083g-page 219 dspic30f ad24 e off offset error 1.25 tbd lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad24a e off offset error 1.25 tbd lsb v inl = av ss = v refl = 0v, av dd = v refh = 3v ad25 monotonicity (1) guaranteed ad26 cmrr common-mode rejection tbd db ad27 psrr power supply rejection ratio tbd db ad28 ctlk channel to channel crosstalk tbd db dynamic performance ad30 thd total harmonic distortion db ad31 sinad signal to noise and distortion tbd db ad32 sfdr spurious free dynamic range tbd db ad33 f nyq input signal bandwidth 50 khz ad34 enob effective number of bits tbd tbd bits table 23-34: 12-bit a/d module specifications (continued) ac characteristics standard operating conditions: 2.7v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min. typ max. units conditions note 1: the a/d conversion result never decr eases with an increase in the in put voltage, and has no missing codes.
dspic30f ds70083g-page 220 preliminary ? 2004 microchip technology inc. figure 23-23: 12-bit a/d conversion timing characteristics (asam = 0 , ssrc = 000 ) ad55 t samp bcf samp bsf samp ad61 adclk instruction samp ch0_dischrg ch0_samp ad60 done adif adres( 0 ) 1 2 3 4 5 6 8 7 1 - software sets adcon. samp to start sampling. 2 - sampling starts after discharge period. 3 - software clears adcon. samp to start conversion. 4 - sampling ends, conversion sequence starts. 5 - convert bit 11 . 9 - one t ad for end of conversion. ad50 eoc 9 6 - convert bit 10 . 7 - convert bit 1 . 8 - convert bit 0 . execution t samp is described in the dspic30f family reference manual , section 18.
? 2004 microchip technology inc. preliminary ds70083g-page 221 dspic30f table 23-35: 12-bit a/d conversion timing requirements ac characteristics standard operating conditions: 2.7v to 5.5v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40 c t a +125c for extended param no. symbol characteristic min. typ max. units conditions clock parameters ad50 t ad a/d clock period 667 ns v dd = 3-5.5v (note 1) ad51 t rc a/d internal rc oscillator period 1.2 1.5 1.8 s conversion rate ad55 t conv conversion time 14 t ad ns ad56 f cnv throughput rate 100 ksps v dd = v ref = 5v ad57 t samp sample time 1 t ad nsv dd = 3-5.5v source resistance r s = 0-2.5 k ? timing parameters ad60 t pcs conversion start from sample trigger t ad ns ad61 t pss sample start from setting sample (samp) bit 0.5 t ad 1.5 t ad ns ad62 t css conversion completion to sample start (asam = 1 ) tbdns ad63 t dpu time to stabilize analog stage from a/d off to a/d on tbd s note 1: because the sample caps will eventually lose char ge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures. 2: these parameters are characterize d but not tested in manufacturing.
dspic30f ds70083g-page 222 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds70083g-page 223 dspic30f 24.0 packaging information 24.1 package marking information xxxxxxxxxxxxxxxxx yywwnnn 28-lead pdip example xxxxxxxxxxxxxxxxx 18-lead pdip example 18-lead soic example 0348017 dspic30f2012-30i/sp xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn dspic30f3012-30i/p 0348017 yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx 0348017 -30i/so dspic30f2011 legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code note : in the event the full microchip part numb er cannot be marked on one line, it will be carried over to the next line thus li miting the number of available characters for customer specific information. * standard device marking consists of microchip part number, year code, week code, and traceability code. for device marking beyond this, certai n price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. 28-lead soic (.300?) xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example pic30f2012-30i/so 0310017
dspic30f ds70083g-page 224 preliminary ? 2004 microchip technology inc. 24.1 package marking information (continued) 44-lead tqfp example xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn dspic30f 3014-30i/pt 0348017 64-lead tqfp (10x10x1mm) example xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn dspic30f 5011-30i/pt 0348017 xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn 64-lead tqfp (14x14x1mm) dspic30f6011 -30i/pf 0348017 example xxxxxxxxxxxxxxxxxx yywwnnn 40-lead pdip example xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx dspic30f3014-30i/p 0348017 xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn dspic30f4013-30i/ml example 0310017
? 2004 microchip technology inc. preliminary ds70083g-page 225 dspic30f 24.1 package marking information (continued) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn 80-lead tqfp (14x14x1mm) dspic30f6013 -30i/pf 0348017 example 80-lead tqfp (12x12x1mm) xxxxxxxxxxxx yywwnnn xxxxxxxxxxxx example dspic30f5013 0348017 -30i/pt
dspic30f ds70083g-page 226 preliminary ? 2004 microchip technology inc. 18-lead plastic dual in-line (p) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.46 1.14 .070 .058 .045 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 22.99 22.80 22.61 .905 .898 .890 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.94 7.62 .325 .313 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb e p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. m old flash or protrusio ns shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-007 significant characteristic
? 2004 microchip technology inc. preliminary ds70083g-page 227 dspic30f 28-lead plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrus ions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. significant characteristic
dspic30f ds70083g-page 228 preliminary ? 2004 microchip technology inc. 18-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.30 0.27 0.23 .012 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 11.73 11.53 11.33 .462 .454 .446 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 18 18 n number of pins max nom min max nom min dimension limits millimeters inches* units l c h 45 1 2 d p n b e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-051 significant characteristic
? 2004 microchip technology inc. preliminary ds70083g-page 229 dspic30f 28-lead plastic small outlin e (so) ? wide, 300 mil (soic) foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include m old flash or protrusions. mold flas h or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic
dspic30f ds70083g-page 230 preliminary ? 2004 microchip technology inc. 40-lead plastic dual in-l ine (p) ? 600 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 52.45 52.26 51.94 2.065 2.058 2.045 d overall length 14.22 13.84 13.46 .560 .545 .530 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 1 2 d n e1 c eb e p l b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-016 significant characteristic
? 2004 microchip technology inc. preliminary ds70083g-page 231 dspic30f 4 4-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-076 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) a a1 a2 e e1 #leads=n1 p b d1 d n 1 2 c l units inches millimeters* dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .03 7 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 ch x 45 significant characteristic
dspic30f ds70083g-page 232 preliminary ? 2004 microchip technology inc. 44-lead plastic quad flat no lead package (ml) 8x8 mm body (qfn)
? 2004 microchip technology inc. preliminary ds70083g-page 233 dspic30f 64-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrus ions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-085 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 0.27 0.22 0.17 .011 .009 .007 b lead width 0.23 0.18 0.13 .009 .007 .005 c lead thickness 16 16 n1 pins per side 10.10 10.00 9.90 .398 .394 .390 d1 molded package length 10.10 10.00 9.90 .398 .394 .390 e1 molded package width 12.25 12.00 11.75 .482 .472 .463 d overall length 12.25 12.00 11.75 .482 .472 .463 e overall width 7 3.5 0 7 3.5 0 foot angle 0.75 0.60 0.45 .030 .024 .018 l foot length 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.05 1.00 0.95 .041 .039 .037 a2 molded package thickness 1.20 1.10 1.00 .047 .043 .039 a overall height 0.50 .020 p pitch 64 64 n number of pins max nom min max nom min dimension limits millimeters* inches units c 2 1 n d d1 b p #leads=n1 e1 e a2 a1 a l ch x 45 (f) footprint (reference) (f) .039 1.00 pin 1 corner chamfer ch .025 .035 .045 0.64 0.89 1.14 significant characteristic
dspic30f ds70083g-page 234 preliminary ? 2004 microchip technology inc. 64-lead plastic thin quad flatpack (pf) 14x14x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrus ions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-085 13 11 mold draft angle bottom 13 11 11 mold draft angle top 0.45 0.32 0.30 .018 .013 .019 b lead width 0.20 0.09 .008 .004 c lead thickness 16 16 n1 pins per side 14.00 .551 d1 molded package length 14.00 .551 e1 molded package width 16.00 .630 d overall length 16.00 .630 e overall width 7 0 7 0 foot angle 0.75 0.60 0.45 .030 .024 .018 l foot length 0.15 0.05 .006 .002 a1 standoff 1.05 1.00 0.95 .041 .039 .037 a2 molded package thickness 1.20 .047 a overall height 0.80 .032 p pitch 64 64 n number of pins max nom min max nom min dimension limits millimeters* inches units c 2 1 n d d1 b p #leads=n1 e1 e a2 a1 a l ch x 45 (f) footprint (reference) (f) .039 1.00 pin 1 corner chamfer ch significant characteristic 11 13 13
? 2004 microchip technology inc. preliminary ds70083g-page 235 dspic30f 80-lead plastic thin quad flatpack (pt) 12x12x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or prot rusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-092 1.10 1.00 .043 .039 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) e e1 #leads=n1 p b d1 d n 1 2 c l a a1 a2 units inches millimeters* dimension limits min nom max min nom max number of pins n 80 80 pitch p .020 0.50 overall height a .047 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .541 .551 .561 13.75 14.00 14.25 overall length d .541 .551 .561 13.75 14.00 14.25 molded package width e1 .463 .472 .482 11.75 12.00 12.25 molded package length d1 .463 .472 .482 11.75 12.00 12.25 pins per side n1 20 20 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .007 .009 .011 0.17 0.22 0.27 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 ch x 45 significant characteristic
dspic30f ds70083g-page 236 preliminary ? 2004 microchip technology inc. 80-lead plastic thin quad flatpack (pf) 14 x14x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or prot rusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-092 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) e e1 #leads=n1 p b d1 d n 1 2 c l a a1 a2 units inches millimeters* dimension limits min nom max min nom max number of pins n 80 80 pitch p .026 0.65 overall height a .047 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .006 0.05 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 0 7 0 7 overall width e .630 16.00 overall length d .630 16.00 molded package width e1 .551 14.00 molded package length d1 . .551 14.00 pins per side n1 20 20 lead thickness c .004 .008 0.09 0.20 lead width b .009 .013 .015 0.22 0.32 0.38 mold draft angle top 11 13 11 13 mold draft angle bottom 11 13 11 13 ch x 45 significant characteristic
? 2004 microchip technology inc. preliminary ds70083g-page 237 dspic30f index numerics 12-bit analog-to-digital converte r (a/d) module .............. 145 a a/d ........................... .................... .................... ................. 145 aborting a conversion ............. .................. ............... 147 adchs register ......... .................. ................ ............ 145 adcon1 register....... .................. ................ ............ 145 adcon2 register....... .................. ................ ............ 145 adcon3 register....... .................. ................ ............ 145 adcssl register ....... .................. ................ ............ 145 adpcfg register....... .................. ................ ............ 145 configuring analog port pins... .................. ......... 76, 150 connection considerations......... .................. ............ 150 conversion operation .............. .................. ............... 146 effects of a reset...... .................. .................. ............ 149 operation during cpu idle mode ................. ............ 149 operation during cpu sleep mode ................ .......... 149 output formats ........... .................. ................ ............ 149 power-down modes ........ ....................... ................... 149 programming the sample trigger.. ............... ............ 147 register map............. .................. .................. ............ 151 result buffer .......... .................. .................. ............... 146 sampling requirements.............. .................. ............ 148 selecting the conversion clock ... ................. ............ 147 selecting the conversion seque nce............. ............ 146 ac characteristics ....... .................... .................. ............... 195 load conditions .......... .................. ................ ............ 195 ac temperature and voltage specif ications .................... 195 ac-link mode operation ............... .................... ............... 142 16-bit mode ............ .................. .................. ............... 142 20-bit mode ............ .................. .................. ............... 142 address generator units ............... .................... ................. 47 alternate vector table ...... .................. .................. .............. 59 analog-to-digital converter. see a/d. assembler mpasm assembler.................. .................. ............... 177 automatic clock stretch.... .................. .................. ............ 110 during 10-bit addressing (stren = 1)......... ............ 110 during 7-bit addressing (stren = 1)........... ............ 110 receive mode ............. .................. ................ ............ 110 transmit mode ....................... .................... ............... 110 b bandgap start-up time requirements.............. .................. ................ ............ 200 timing characteristics ............. .................. ............... 200 barrel shifter ................ .................... ..................... .............. 33 bit reversed addressing example .................... .................. .................. .............. 54 implementation ........... .................. .................. ............ 53 bit-reversed addressing ............... .................... ................. 53 modifier values table .............. ..................... .............. 54 sequence table (16-entry)........... .................. ............ 54 block diagrams 12-bit a/d functional ............... .................. ............... 145 16-bit timer1 module ............... ..................... .............. 81 16-bit timer2............. .................. .................. .............. 87 16-bit timer3............. .................. .................. .............. 87 16-bit timer4............. .................. .................. .............. 92 16-bit timer5............. .................. .................. .............. 92 32-bit timer2/3....................... .................... ................. 86 32-bit timer4/5....................... .................... ................. 91 can buffers and protocol engi ne ............... ............. 124 dci module................ .................. ................ ............. 136 dedicated port structure ........... .................. ............... 75 dsp engine ............... .................. .................. ............. 29 dspic30f5013/6013/6014 ....................... ................... 18 external power-on reset circui t ................. ............. 162 i 2 c .................. .................... ..................... ................. 108 input capture mode................. .................... ............... 95 oscillator system................... .................... ............... 155 output compare mode .............. .................. ............... 99 reset system ............ .................. ................ ............. 159 shared port structure... .................. ............... ............. 76 spi.................. .................... ..................... ................. 104 spi master/slave connection...... ................ ............. 104 uart receiver.......... .................. ................ ............. 116 uart transmitter...... .................. ................ ............. 115 bor characteristics ...... .................. .................. ............... 194 bor. see brown-out reset. brown-out reset characteristics......... .................. .................. ............. 193 timing requirements ................ .................. ............. 200 c c compilers mplab c17............... .................. ................ ............. 178 mplab c18............... .................. ................ ............. 178 mplab c30............... .................. ................ ............. 178 can module ........... .................... ..................... ................. 123 baud rate setting ..... .................. ................ ............. 128 can1 register map... .................. ................ ............. 130 can2 register map... .................. ................ ............. 132 frame types ............. .................. ................ ............. 123 i/o timing characteristics ....... .................. ............... 217 message reception........ ...................... .................... 126 message transmission.............. .................. ............. 127 modes of operation ... .................. ................ ............. 125 overview.................. .................. .................. ............. 123 clkout and i/o timing characteristics......... .................. .................. ............. 198 requirements ............ .................. ................ ............. 198 code examples data eeprom block erase ....... ................. ............... 70 data eeprom block write ....... .................. ............... 72 data eeprom read.... .................. ............... ............. 69 data eeprom word erase ....... ................. ............... 70 data eeprom word write ....... .................. ............... 71 erasing a row of program memo ry .............. ............. 65 initiating a programming sequence . ................ .......... 66 loading write latches...... ....................... ................... 66 code protection ............. .................. .................. ............... 153 core architecture......... .................... .................... ............... 21 overview.................. .................. .................. ............... 21 d data accumulators and adder/subt ractor ........... ............... 31 data space write saturation ...... ................. ............... 33 overflow and saturation .......... .................... ............... 31 round logic .............. .................. .................. ............. 32 write back ............... .................. .................. ............... 32 data address space........ .................. .................. ............... 39 alignment................. .................. .................. ............... 40 alignment (figure) ..... .................. .................. ............. 40 effect of invalid memory acce sses (table) ................ 40 mcu and dsp (mac class) instructions example .... 43 memory map.............. .................. .................. ............. 40 near data space ....... .................. .................. ............. 41
dspic30f ds70083g-page 238 preliminary ? 2004 microchip technology inc. sample memory map ................. .................. ............... 42 software stack ...................... .................... .................. 41 spaces .............. .................... .................... .................. 39 width................. .................... .................... .................. 40 data converter interface (dci) m odule ............... ............. 135 data eeprom memory .................. ..................... ............... 69 erasing .............. .................... .................... .................. 70 erasing, block .......... .................. .................. ............... 70 erasing, word .......... .................. .................. ............... 70 protection against spurious writ e ................. ............. 73 reading............. .................... .................... .................. 69 write verify .............. .................. .................. ............... 73 writing ............... .................... .................... .................. 71 writing, block ........... .................. .................. ............... 72 writing, word ........... .................. .................. ............... 71 data space organization .............. .................... .................. 47 dc characteristics ........ .................. .................. ................ 184 bor ...................... .................. .................. ................ 194 brown-out reset ........ .................. ................ ............. 193 i/o pin input specifications ..... .................. ................ 191 i/o pin output specifications .. .................. ................ 192 idle current (i idle ) .................. .................. ................ 187 low-voltage detect...... ................ ................ ............. 192 lvdl ..................... .................. .................. ................ 193 operating current (i dd )....................... ............. ......... 185 power-down current (i pd ) .................... .................... 189 program and eeprom................ ................ ............. 194 temperature and voltage specif ications ....... ........... 184 dci module bit clock generator................. .................. ................ 139 buffer alignment with data frames ...... .................... 140 buffer control ...................... .................... .................. 135 buffer data alignment ............. .................. ................ 135 buffer length control. .................. ................ ............. 140 cofs pin................. .................. .................. ............. 135 csck pin................. .................. .................. ............. 135 csdi pin ............... .................. .................. ................ 135 csdo mode bit ......... .................. ................ ............. 141 csdo pin ................ .................. .................. ............. 135 data justification control bit ... .................. ................ 139 device frequencies for common codec csck frequen- cies (table) .......... ................ ................ ............. 139 digital loopback mode .. ....................... .................... 141 enable...................... .................. .................. ............. 137 frame sync generator .............. .................. ............. 137 frame sync mode control bits .. .................. ............. 137 i/o pins ................. .................. .................. ................ 135 interrupts ............... .................. .................. ................ 141 introduction ................ .................. ................ ............. 135 master frame sync operation ... .................. ............. 137 operation ................. .................. .................. ............. 137 operation during cpu idle mode ................ ............. 142 operation during cpu sleep mode ............... ........... 142 receive slot enable bits......... .................. ................ 140 receive status bits ............... .................... ................ 141 register map............ .................. .................. ............. 143 sample clock edge control bit... ................. ............. 139 slave frame sync operation ..... .................. ............. 138 slot enable bits operation with frame sync ............ 140 slot status bits...... .................. .................. ................ 141 synchronous data transfers ....... ................ ............. 140 timing characteristics ac-link mode ........ ....................... .................... 207 multichannel, i 2 s modes ............... .................... 205 timing requirements ac-link mode........ ...................... ..................... 207 multichannel, i 2 s modes.............. ..................... 206 transmit slot enable bits ......... .................. .............. 139 transmit status bits..... ............... ................ .............. 141 transmit/receive shift register ................. .............. 135 underflow mode control bit....... ................. .............. 141 word size selection bits ........ .................. ................ 137 demonstration boards picdem 1................. .................. ................ .............. 180 picdem 17............... .................. ................ .............. 180 picdem 18r pic18c601/801....... ............... ............ 181 picdem 2 plus............ ............... ................ .............. 180 picdem 3 pic16c92x.... ....................... .................. 180 picdem 4................. .................. ................ .............. 180 picdem lin pic16c43x .. ..................... .................. 181 picdem usb pic16c7x5 ......... ................ .............. 181 picdem.net internet/ethernet .... ................ .............. 180 development support ....... .................. ................ .............. 177 device configuration register map ............ .................. ................ .............. 168 device configuration registers fborpor ................ .................. ................ .............. 166 fgs ...................... .................. .................. ................ 166 fosc............... ..................... .................... ................ 166 fwdt ..................... .................. .................. .............. 166 device overview........... .................... .................. ............... 17 disabling the uart ...... .................. .................. ................ 117 divide support .............. .................... .................. ................ 27 instructions (table) ... .................. .................. .............. 27 dsp engine .................. .................... .................. ................ 28 multiplier .......... ..................... .................... .................. 30 dual output compare match mode .................. ................ 100 continuous pulse mode............ .................. .............. 100 single pulse mode.... .................. ................ .............. 100 e electrical characteristics ........... ..................... .................. 183 ac.................. .................... ..................... .................. 195 dc ................. .................... ..................... .................. 184 enabling and setting up uart alternate i/o ........... .................. .................. .............. 117 setting up data, parity and stop bit selections ....... 117 enabling the uart ......... .................. .................. .............. 117 equations a/d conversion clock............. .................. ................ 147 baud rate................. .................. ................ .............. 119 bit clock frequency..... ............... ................ .............. 139 cofsg period...... .................. .................. ................ 137 serial clock rate ...... .................. ................ .............. 112 time quantum for clock gener ation .......... .............. 129 errata ....................... ..................... .................... .................. 16 evaluation and programming tools... ................. .............. 181 exception processing ................... .................... .................. 55 external clock timing characteristics type a, b and c timer ............. .................. .............. 201 external clock timing requirement s ................. .............. 196 type a timer ............ .................. ................ .............. 201 type b timer ............ .................. ................ .............. 202 type c timer ............ .................. ................ .............. 202 external interrupt requests .......... .................... .................. 60
? 2004 microchip technology inc. preliminary ds70083g-page 239 dspic30f f fast context saving...... ................... ..................... .............. 60 flash program memory .... .................. .................. .............. 63 control registers ........ .................. .................. ............ 64 nvmadr ................ ................ ................ ............ 64 nvmadru................. ...................... ................... 64 nvmcon ................... ...................... ................... 64 nvmkey................. ................ ................ ............ 64 i i/o pin specifications input ....................... .................. .................. ............... 191 output .................... .................. .................. ............... 192 i/o ports ..................... .................... .................... ................. 75 parallel (pio) ............ .................. .................. .............. 75 i 2 c ..................... ...................... ....................... ................... 107 i 2 c 10-bit slave mode operation ..... .................. ............... 109 reception............... .................. .................. ............... 110 transmission............... .................. ................ ............ 109 i 2 c 7-bit slave mode operation ....... .................. ............... 109 reception............... .................. .................. ............... 109 transmission............... .................. ................ ............ 109 i 2 c master mode operation ........... .................... ............... 111 baud rate generator.. .................. ................ ............ 112 clock arbitration........ .................. .................. ............ 112 multi-master communication, bus collision and bus arbitration ............... ................ ............ 112 reception............... .................. .................. ............... 111 transmission............... .................. ................ ............ 111 i 2 c master mode support ... .................. ................ ............ 111 i 2 c module ............... .................... .................... ................. 107 addresses ................. .................. .................. ............ 109 bus data timing characteristics master mode ........... ....................... ................... 213 slave mode ............. ....................... ................... 215 bus data timing requirements master mode ........... ....................... ................... 214 slave mode ............. ....................... ................... 216 bus start/stop bits timing characteristics master mode ........... ....................... ................... 213 slave mode ............. ....................... ................... 215 general call address support .... .................. ............ 111 interrupts................ .................. .................. ............... 110 ipmi support ............... .................. ................ ............ 111 operating function description .... ................ ............ 107 operation during cpu sleep and idle modes .......... 112 pin configuration ........ .................. ................ ............ 107 programmer?s model................ .................. ............... 107 register map............. .................. .................. ............ 113 registers................ .................. .................. ............... 107 slope control .............. .................. ................ ............ 111 software controlled clock str etching (stren = 1).. 110 various modes ............ .................. ................ ............ 107 i 2 s mode operation .......... .................. .................. ............ 142 data justification.... .................. .................. ............... 142 frame and data word length sele ction................... 142 idle current (i idle ) ..................... ...................... ................. 187 in-circuit serial programming (icsp) ......................... 63, 153 input capture (capx) timing char acteristics .................. 203 input capture module ....... .................. .................. .............. 95 interrupts................... .................. .................. .............. 97 register map............. .................. .................. .............. 98 input capture operation duri ng sleep and idle modes ...... 97 cpu idle mode.......... .................. .................. .............. 97 cpu sleep mode .......... .................. ................ ............ 97 input capture timing requirements. ................. ............... 203 input change notification module................. .............. ........ 79 register map (bits 15-8).......... .................... ............... 79 register map (bits 7-0)............ .................... ............... 79 instruction addressing modes ....... .................... ................. 47 file register instructions ......... .................... ............... 48 fundamental modes supported ..... ............... ............. 47 mac instructions ..................... .................... ............... 48 mcu instructions ..................... .................... ............... 48 move and accumulator instructi ons .............. ............. 48 other instructions ...... .................. .................. ............. 48 instruction flow............ .................... .................... ............... 24 pipeline 1-word, 1-cycle (figure) ..... .................. ............. 24 1-word, 2-cycle (figure) ..... .................. ............. 24 1-word, 2-cycle mov.d operations (figure)..... 25 1-word, 2-cycle table operations (figure) ....... 25 1-word, 2-cycle with instruction stall (figure) ... 26 2-word, 2-cycle do, dow (f igure)......... .......... 26 2-word, 2-cycle goto, call (figure) ............. 25 instruction set overview.................. .................. .................. ............. 172 summary ............. .................... .................. ............... 169 instruction stalls .......... .................... .................... ............... 49 introduction.............. .................. .................. ............... 49 raw dependency detection ........... ............... ............. 49 inter-integrated circuit. see i 2 c. internal clock timing examples ...... .................. ............... 197 interrupt controller register map ........... .................. .................. ............... 61 interrupt priority ........... .................... .................... ............... 56 interrupt sequence .......... .................. .................. ............... 59 interrupt stack frame.............. .................... ............... 59 interrupts ............ ...................... ....................... ................... 55 l load conditions............. .................. .................. ............... 195 low voltage detect (lvd) . .................. ................ ............. 165 low-voltage detect characteristics.. ................. ............... 192 lvdl characteristics ..... .................. .................. ............... 193 m memory organization ...... .................. .................. ............... 17 core register map .... .................. .................. ............. 43 modes of operation disable................... .................. .................. ............... 125 initialization............ .................. .................. ............... 125 listen all messages................. .................. ............... 125 listen only............... .................. .................. ............. 125 loopback ................... .................. ................ ............. 125 normal operation .................... .................. ............... 125 modulo addressing ........ .................... .................. ............... 50 applicability.............. .................. .................. ............... 53 decrementing buffer operation example................... 52 incrementing buffer operation example ....... ............. 51 restrictions.............. .................. .................. ............... 53 start and end address ... ................ ............... ............. 50 w address register selection... .................. ............... 51 mplab asm30 assembler, linker, librarian ................... 178 mplab icd 2 in-circuit debugger .... .................. ............. 179 mplab ice 2000 high performance universal in-circuit emulator................... .................. ............... 179 mplab ice 4000 high performance universal in-circuit emulator................... .................. ............... 179
dspic30f ds70083g-page 240 preliminary ? 2004 microchip technology inc. mplab integrated development environment software .. 177 mplink object linker/mplib ob ject librarian ................ 178 multiplier 16-bit integer and fractional modes example ............ 30 n nvm register map............ .................. .................. ............... 67 o oc/pwm module timing characteris tics............. ............. 204 operating current (i dd )................... .................. ................ 185 operating frequency vs voltage dspic30fxxxx-20 (extended).... ................ ............. 184 oscillator configurations .......... .................. .................. ............. 156 fail-safe clock monitor........ ................ ............. 158 fast rc (frc) ................... .................. ............. 157 initial clock source selectio n .............. ............. 156 low power rc (lprc) ........ ................ ............. 158 lp oscillator control .......... .................. ............. 157 phase locked loop (pll) ....... .............. ........... 157 start-up timer (ost) ........... ................ ............. 157 operating modes (table) ........... .................. ............. 154 system overview ....... .................. ................ ............. 153 oscillator selection ....... .................. .................. ................ 153 oscillator start-up timer timing characteristics ............ .................. ................ 199 timing requirements ................. .................. ............. 200 output compare interrupts ........... .................... ................ 101 output compare module............... .................... .................. 99 register map............ .................. .................. ............. 102 timing characteristics ............ .................. ................ 203 timing requirements ................. .................. ............. 203 output compare operation during cpu idle mode.......... 101 output compare sleep mode operat ion.............. ............. 101 p packaging information ....... .................. ................ ............. 223 marking ................. .................. .................. ................ 223 peripheral module disable (pmd) registers .................... 167 pickit 1 flash starter kit........... ...................... .................. 181 picstart plus development pr ogrammer ........ ............. 179 pinout descriptions ....................... .................... .................. 19 pll clock timing specifications.... ................... ................ 197 por. see power-on reset. port write/read example. .................. .................. ............... 76 porta register map ...... .................. .................. ............... 77 portb register map ...... .................. .................. ............... 77 portc register map ...... .................. .................. ............... 77 portd register map ...... .................. .................. ............... 77 portf register map....... .................. .................. ............... 78 portg register map ...... .................. .................. ............... 78 power saving modes ......... .................. ................ ............. 165 idle .................. .................... .................... .................. 166 sleep..................... .................. .................. ................ 165 sleep and idle ............ .................. ................ ............. 153 power-down current (i pd ) ................. .................. ............. 189 power-up timer timing characteristics ............ .................. ................ 199 timing requirements ................. .................. ............. 200 pro mate ii universal device programmer ................... 179 program address space ............... .................... .................. 35 alignment and data access using table instructions........... .................. ................ ............. 36 construction ............. .................. .................. ............... 35 data access from, address g eneration ....... .............. 35 data space window into operat ion.............. .............. 38 data table access (ls word) .... .................. .............. 36 data table access (ms byte)..... .................. .............. 37 memory map............. .................. .................. .............. 39 table instructions tblrdh ........... .................. .................. .............. 36 tblrdl................. ................ ............... .............. 36 tblwth.................. ....................... .................... 36 tblwtl .................. ....................... .................... 36 visibility from data space....... .................... ................ 37 program and eeprom characteristi cs.............. .............. 194 program counter ............ .................. .................. ................ 22 programmable .............. .................. .................. ................ 153 programmer?s model ........ .................. .................. .............. 22 diagram .............. .................... .................... ................ 23 programming operations..... .................. ............... .............. 65 algorithm for program flash..... .................. ................ 65 erasing a row of program memo ry.............. .............. 65 initiating the programming seq uence........... .............. 66 loading write latches .............. .................. ................ 66 protection against accidental writes to osccon ........... 159 r reset ................. ...................... .................... ............. 153, 159 bor, programmable ..... ...................... ..................... 162 brown-out reset (bor)............ .................. .............. 153 oscillator start-up timer (ost) . ................. .............. 153 por operating without fscm an d pwrt................ 162 with long crystal start-up time .......... ............ 162 por (power-on reset)............. .................. .............. 160 power-on reset (por)............. .................. .............. 153 power-up timer (pwrt) .......... .................. .............. 153 reset sequence ............. .................. .................. ................ 57 reset sources ............. .................. ............... .............. 57 reset sources brown-out reset (bor)............ .................. ................ 57 illegal instruction trap ............ .................... ................ 57 trap lockout................ .................. ............... .............. 57 uninitialized w register trap .... ................. ................ 57 watchdog time-out ....... ................ ............... .............. 57 reset timing characteristics........ .................... ................ 199 reset timing requirements ........... .................. ................ 200 rtsp operation ............. .................. .................. ................ 64 run-time self-programming (rtsp) . .................. .............. 63 s serial peripheral interface. see spi. simple capture event mode........... .................... ................ 96 buffer operation ....... .................. .................. .............. 96 hall sensor mode ................... .................... ................ 96 prescaler ................ .................. .................. ................ 96 timer2 and timer3 selection mo de.............. .............. 96 simple oc/pwm mode timing r equirements ................. 204 simple output compare match m ode ................ .............. 100 simple pwm mode ......... .................. .................. .............. 100 input pin fault protection ......... .................. .............. 100 period ................... .................. .................. ................ 101 software simulator (mplab sim) .. .................. ................ 178 software simulator (mplab sim30) .................. .............. 178 software stack pointer, frame po inter .............. ................ 22 call stack frame ...... .................. ............... .............. 41 spi ..................... ...................... ....................... .................. 103 spi module ................... .................. .................. ................ 103 framed spi support ...... ...................... ..................... 103
? 2004 microchip technology inc. preliminary ds70083g-page 241 dspic30f operating function description .... ................ ............ 103 operation during cpu idle mode ................. ............ 105 operation during cpu sleep mode ................ .......... 105 sdox disable ........................ .................... ............... 103 slave select synchronization ..... .................. ............ 105 spi1 register map................... .................. ............... 106 spi2 register map................... .................. ............... 106 timing characteristics master mode (cke = 0) ...... .................. ............ 208 master mode (cke = 1) ...... .................. ............ 209 slave mode (cke = 1) .......... .................... 210, 211 timing requirements master mode (cke = 0) ...... .................. ............ 208 master mode (cke = 1) ...... .................. ............ 209 slave mode (cke = 0) .......... ................ ............ 210 slave mode (cke = 1) .......... ................ ............ 212 word and byte communication .... ................ ............ 103 status bits, their significance and the initialization condition for rcon register, ca se 1 .......... ............ 163 status bits, their significance and the initialization condition for rcon register, ca se 2 .......... ............ 164 status register ............ .................... ..................... .............. 22 z status bit ............... .................. .................. .............. 22 symbols used in opcode description s................. ............ 170 system integration ....... .................... .................. ............... 153 register map............. .................. .................. ............ 168 t table instruction operation summary .................. .............. 63 temperature and voltage specifications ac .................... .................... .................... ................. 195 dc............... ....................... ...................... ................. 184 timer1 module ............. .................... ..................... .............. 81 16-bit asynchronous counter m ode ............... ............ 81 16-bit synchronous counter mode ................. ............ 81 16-bit timer mode....... .................. .................. ............ 81 gate operation ...................... .................... ................. 82 interrupt.............. .................... .................... ................. 82 operation during sleep mode ...... .................. ............ 82 prescaler................... .................. .................. .............. 82 real-time clock ........... .................. ................ ............ 82 interrupts............... .................. ................ ............ 83 oscillator operation ............ .................. .............. 83 register map............. .................. .................. .............. 84 timer2 and timer3 selection mode ................... ............... 100 timer2/3 module ............ ..................... .................. .............. 85 16-bit timer mode....... .................. .................. ............ 85 32-bit synchronous counter mode ................. ............ 85 32-bit timer mode....... .................. .................. ............ 85 adc event trigger........ .................. ................ ............ 88 gate operation ...................... .................... ................. 88 interrupt.............. .................... .................... ................. 88 operation during sleep mode ...... .................. ............ 88 register map............. .................. .................. .............. 89 timer prescaler...................... .................... ................. 88 timer4/5 module ............ ..................... .................. .............. 91 register map............. .................. .................. .............. 93 timing characteristics a/d conversion 10-bit (asam = 0, ssrc = 000)............. .......... 220 bandgap start-up time............... .................. ............ 200 can module i/o.......... .................. ................ ............ 217 clkout and i/o......... .................. ................ ............ 198 dci module ac-link mode ......... ....................... ................... 207 multichannel, i 2 s modes ................ ................... 205 external clock ........... .................. ................ ............. 195 i 2 c bus data master mode........... ...................... .................... 213 slave mode ....................... .................. ............. 215 i 2 c bus start/stop bits master mode........... ...................... .................... 213 slave mode ....................... .................. ............. 215 input capture (capx)..... ...................... .................... 203 oc/pwm module.......... ............... ................ ............. 204 oscillator start-up timer.......... .................. ............... 199 output compare module ........... .................. ............. 203 power-up timer ......... .................. ................ ............. 199 reset ..................... .................. .................. ............... 199 spi module master mode (cke = 0)....... ................ ............. 208 master mode (cke = 1)....... ................ ............. 209 slave mode (cke = 0)......... ................ ............. 210 slave mode (cke = 1)......... ................ ............. 211 type a, b and c timer external clock........ ............. 201 watchdog timer ...................... .................. ............... 199 timing diagrams can bit.................. .................. .................. ............... 128 frame sync, ac-link start of frame .......... ............. 138 frame sync, multi-channel mode ............... ............. 138 i 2 s interface frame sync .......... .................. ............. 138 pwm output .............. .................. ................ ............. 101 time-out sequence on power-up (mclr not tied to v dd ), case 1 ...... ............... 160 time-out sequence on power-up (mclr not tied to v dd ), case 2 ...... ............... 161 time-out sequence on power-up (mclr tied to v dd ) ..................... .................... 160 timing diagrams and specifications dc characteristics - internal rc accuracy .............. 197 timing diagrams.see timing characteristics timing requirements a/d conversion 10-bit ................. .................. ................ ............. 221 bandgap start-up time .... ....................... ................. 200 brown-out reset.................... .................... ............... 200 clkout and i/o ............ ...................... .................... 198 dci module ac-link mode......... ...................... .................... 207 multichannel, i 2 s modes............... .................... 206 external clock ........... .................. ................ ............. 196 i 2 c bus data (master mode) ...... ................. ............. 214 i 2 c bus data (slave mode) ....... .................. ............. 216 input capture........... .................. .................. ............. 203 oscillator start-up timer.......... .................. ............... 200 output compare module ........... .................. ............. 203 power-up timer ......... .................. ................ ............. 200 reset ..................... .................. .................. ............... 200 simple oc/pwm mode ............. .................. ............. 204 spi module master mode (cke = 0)....... ................ ............. 208 master mode (cke = 1)....... ................ ............. 209 slave mode (cke = 0)......... ................ ............. 210 slave mode (cke = 1)......... ................ ............. 212 type a timer external clock.... ................. ............... 201 type b timer external clock.... ................. ............... 202 type c timer external clock... .................. ............... 202 watchdog timer ...................... .................. ............... 200 timing specifications pll clock .................. .................. ................ ............. 197
dspic30f ds70083g-page 242 preliminary ? 2004 microchip technology inc. traps .................. ....................... ...................... .................... 57 hard and soft ............. .................. .................. ............. 58 sources .................... .................. .................. ............... 57 address error trap .............. .................. ............. 58 math error trap...... ................ ................ ............. 57 oscillator fail trap. ................ ................ ............. 58 stack error trap................... .................. ............. 58 u uart module address detect mode ............. .................. ................ 119 auto baud support..... .................. ................ ............. 120 baud rate generator .............. .................. ................ 119 enabling and setting up ............ .................. ............. 117 framing error (ferr)............. .................. ................ 119 idle status ............. .................. .................. ................ 119 loopback mode ............. ....................... .................... 119 operation during cpu sleep and idle modes .......... 120 overview .................. .................. .................. ............. 115 parity error (perr) ................ .................. ................ 119 receive break....................... .................... ................ 119 receive buffer (uxrxb) ............ .................. ............. 118 receive buffer overrun erro r (oerr bit) ... ............. 118 receive interrupt........ .................. ................ ............. 118 receiving data........... .................. ................ ............. 118 receiving in 8-bit or 9-bit da ta mode........ ................ 118 reception error handling........ .................. ................ 118 transmit break ............ ............... ................ .............. 118 transmit buffer (uxtxb) .......... .................. .............. 117 transmit interrupt ................... .................. ................ 118 transmitting data ................... .................. ................ 117 transmitting in 8-bit data mode .................. .............. 117 transmitting in 9-bit data mode .................. .............. 117 uart1 register map... ............... ................ .............. 121 uart2 register map... ............... ................ .............. 121 uart operation idle mode ................ .................. .................. .............. 120 sleep mode .............. .................. ................ .............. 120 unit id locations ........ .................... .................. ................ 153 universal asynchronous receiver transmitter. see uart. w wake-up from sleep ..... .................. .................. ................ 153 wake-up from sleep and idle ......... .................... ................ 60 watchdog timer timing characteristics ............ .................. ................ 199 timing requirements..... ...................... ..................... 200 watchdog timer (wdt)................ .................. .......... 153, 165 enabling and disabling ............. .................. .............. 165 operation ................ .................. .................. .............. 165 www, on-line support ...... .................. ............... .............. 16
? 2004 microchip technology inc. preliminary ds70083g-page 243 dspic30f on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is av ailable by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may downlo ad files for the latest development tools, data sheets, application notes, user's guides, articles an d sample programs. a vari- ety of microchip specific bu siness information is also available, including listings of microchip sales offices, distributors and factory r epresentatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ? device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development systems, technical information and more ? listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of th e latest versions of all of microchip's development systems software products. plus, this line provides in formation on how customers can receive the most curren t upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. an d most of canada, and 1-480-792-7302 for the rest of the world. 042003
dspic30f ds70083g-page 244 preliminary ? 2004 microchip technology inc. reader response it is our intention to provide yo u with the best documentation possible to en sure successful use of your microchip prod- uct. if you wish to provide your comm ents on organization, clarity, subject matt er, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us wi th your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _ ________ - _________ ds70083g dspic30f 1. what are the best features of this document? 2. how does this document meet your ha rdware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or mislead ing information (what and where)? 7. how would you improve this document?
? 2004 microchip technology inc. preliminary ds70083g-page 245 dspic30f product identification system to order or obtain information, e.g ., on pricing or delivery, refer to the factory or the list ed sales office. examples: a) dspic30f2011at-e/so = extended temp., soic package, rev. a. b) dspic30f5011at-i/pt = industria l temp., tqfp package, rev. a. c) dspic30f3012at-i/p = industri al temp., dip package, rev. a. dspic30f4013at-30i/ p-es trademark architecture flash e = extended high temp -40c to +125c i = industrial -40c to +85c temperature device id package pt = tqfp 10x10 pt = tqfp 12x12 pf = tqfp 14x14 p=dip so = soic sp = spdip ml = qfn 6x6 or 8x8 s = die (waffle pack) w = die (wafers) memory size in bytes 0 = romless 1 = 1k to 6k 2 = 7k to 12k 3 = 13k to 24k 4 = 25k to 48k 5 = 49k to 96k 6 = 97k to 192k 7 = 193k to 384k 8 = 385k to 768k 9 = 769k and up custom id (3 digits) or t = tape and reel a,b,c? = revision level engineering sample (es) speed 20 = 20 mips 30 = 30 mips
ds70083g-page 246 preliminary ? 2004 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: www.microchip.com atlanta alpharetta, ga tel: 770-640-0034 fax: 770-640-0307 boston westford, ma tel: 978-692-3848 fax: 978-692-3821 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 san jose mountain view, ca tel: 650-215-1444 fax: 650-961-0286 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8676-6200 fax: 86-28-8676-6599 china - fuzhou tel: 86-591-750-3506 fax: 86-591-750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen tel: 86-755-8290-1380 fax: 86-755-8295-1393 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - qingdao tel: 86-532-502-7355 fax: 86-532-502-7205 asia/pacific india - bangalore tel: 91-80-2229-0061 fax: 91-80-2229-0062 india - new delhi tel: 91-11-5160-8632 fax: 91-11-5160-8632 japan - kanagawa tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - kaohsiung tel: 886-7-536-4816 fax: 886-7-536-4817 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 taiwan - hsinchu tel: 886-3-572-9526 fax: 886-3-572-6459 europe austria - weis tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark - ballerup tel: 45-4420-9895 fax: 45-4420-9910 france - massy tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - ismaning tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 england - berkshire tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 08/24/04

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